revision-P04, ' 98.12.16
MITSUBISHI LSIs
M5M5V416BTP,RT
DESCRIPTION
The M5M5V416B is a f amily of low v oltage 4-Mbit static RAMs
organized as 262,144-words by 16-bit, f abricated by Mitsubishi's
high-perf ormance 0.25µm CMOS technology .
The M5M5V416B is suitable f or memory applications where a
simple interf acing , battery operating and battery backup are the
important design objectiv es.
M5M5V416BTP,RT are packaged in a 44-pin 400mil thin small
outline package. M5M5V416BTP (normal lead bend ty pe package)
, M5M5V416BRT (rev erse lead bend ty pe package) , both ty pes
are v ery easy t o design a printed circuit board.
From the point of operating temperature, the f amily is div ided into
three v ersions; "Standard", "W-v ersion", and "I-v ersion". Those are
summarized in the part name table below.
Version,
Operating
temperature
Part name
M5M5V416BTP , RT -70L
M5M5V416BTP , RT -85L
PRELIMINARY
FEATURES
Notice: This is not a final specification.
Some parametric limits are subject to change
4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM
Single +2.7~+3.6V power supply
Small stand-by current: 0.3µA(3V,ty p.)
No clocks, No ref resh
Data retention supply v oltage=2.0V to 3.6V
All inputs and outputs are TTL compatible.
Easy memory expansion by S1, S2, BC1 and BC2
Common Data I/O
Three-state outputs: OR-tie capability
OE prev ents data contention in the I/O bus
Process technology : 0.25µm CMOS
Package: 44 pin 400mil TSOP (II)
Stand-by c urrent Icc
(PD)
, Vcc=3.0V
Activ e
current
Ratings (max.)
Icc1
25°C 40°C 70°C 85°C (3.0V, ty p.)
---
---
20µA
---
Power
Supply
Access time
ty pical *
25°C
---
40°C
---
max.
70ns
85ns
100ns
70ns
85ns
100ns
70ns
85ns
100ns
70ns
85ns
100ns
70ns
85ns
100ns
70ns
85ns
100ns
Standard
0 ~ +70°C
M5M5V416BTP , RT -10L
M5M5V416BTP , RT -70H
M5M5V416BTP , RT -85H
M5M5V416BTP , RT -10H
M5M5V416BTP , RT -70LW
M5M5V416BTP , RT -85LW
2.7 ~ 3.6V
2.7 ~ 3.6V
2.7 ~ 3.6V
0.3µA 1µA
1µA
3µA
10µA
---
---
---
---
---
20µA 40µA
40mA
(10MHz)
5mA
(1MHz)
W-
v ersion
M5M5V416BTP , RT -10LW
RT -70HW
M5M5V416BTP , RT -85HW
M5M5V416BTP , RT -10HW
M5M5V416BTP , RT -70LI
M5M5V416BTP , RT -85LI
-20 ~ +85°C
M5M5V416BTP ,
2.7 ~ 3.6V
0.3µA 1µA
---
---
1µA
---
3µA
---
10µA 20µA
20µA 40µA
I-
v ersion
2.7 ~ 3.6V
M5M5V416BTP , RT -10LI
RT -70HI
M5M5V416BTP , RT -85HI
M5M5V416BTP , RT -10HI
-40 ~ +85°C
M5M5V416BTP ,
2.7 ~ 3.6V
0.3µA 1µA
1µA
3µA
10µA 20µA
PIN CONFIGURATION
A4
A3
A2
A1
A0
S1
DQ1
DQ2
DQ3
DQ4
Vcc
GND
DQ5
DQ6
DQ7
DQ8
WE
A15
A14
A13
A12
A16
* "ty pical" parameter is sampled, not 100% tested.
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
BC2
BC1
DQ16
DQ15
DQ14
DQ13
GND
Vcc
DQ12
DQ11
DQ10
DQ9
S2
A8
A9
A10
A11
A17
A5
A6
A7
OE
BC2
BC1
DQ16
DQ15
DQ14
DQ13
GND
Vcc
DQ12
DQ11
DQ10
DQ9
S2
A8
A9
A10
A11
A17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
A4
A3
A2
A1
A0
S1
DQ1
DQ2
DQ3
DQ4
Vcc
GND
DQ5
DQ6
DQ7
DQ8
WE
A15
A14
A13
A12
A16
Pin
A0 ~ A17
S1
S2
W
OE
BC1
BC2
Vcc
GND
Function
Address input
Chip select input 1
Chip select input 2
Write control input
Output enable input
Lower By te (DQ1 ~ 8)
Upper By te (DQ9 ~ 16)
Power supply
Ground supply
DQ1 ~ DQ16 Data input / output
44P3W-H
44P3W-J
Outline:
44P3W-H/J
NC: No Connection
MITSUBISHI ELECTRIC
1
revision-P04, ' 98.12.16
MITSUBISHI LSIs
M5M5V416BTP,RT
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM
FUNCTION
The M5M5V416BTP,RT are organized as 262,144-words
by 16-bit. These dev ices operate on a single +2.7~3.6V
power supply , and are directly TTL compatible to both
input and output. Its f ully static circuit needs no clocks
and no ref resh, and makes it usef ul.
The operation mode are determined by a combination of
the dev ice control inputs BC1 , BC2 , S1, S2 , W and OE.
Each mode is summarized in the f unction table.
A write operation is executed whenev er the low lev el W
ov erlaps with the low lev el BC1 and/or BC2 and the low
lev el S1 and the high lev el S2. The address(A0~A17) must
be set up bef ore the write cy cle and must be stable during
the entire cycle.
A read operation is executed by s etting W at a high lev el
and OE at a low lev el while BC1 and/or BC2 and S1 and
S2 are in an activ e state(S1=L,S2=H).
When setting BC1 at the high lev el and other pins are in
an activ e stage , upper-by t e are in a selectable mode in
which both reading and writing are enabled, and lower-by t e
are in a non-selectable mode. And when setting BC2 at a
high lev el and other pins are in an activ e stage, lower-
by t e are in a selectable mode and upper-by te are in a
non-selectable mode.
When setting BC1 and BC2 at a high lev el or S1 at a high
lev el or S2 at a low lev el, the chips are in a non-selectable
mode in which both reading and writing are disabled. In this
mode, the output stage is in a high-impedance state, allowing
OR-tie with other chips and memory expansion by BC1, BC2
and S1, S2.
The power supply c urrent is reduced as low as 0.3µA(25°C,
ty pical), and the memory data can be held at +2V power
supply , enabling battery back-up operation during power
f ailure or power-down operation in the non-selected mode.
FUNCTION TABLE
S1
H
L
H
X
L
L
L
L
L
L
L
L
L
S2 BC1 BC2 W OE
X
X X
L X
L X
X
X X
H X
X
X X
X H
H
X X
H L
H
L X
H L
H
H L
H L
H
H H
H H
L
L
X
H H
L
H L
H H
L
H H
H L
L
L X
H L
L
H L
H L
L
H H
Mode
Non selection
Non selection
Non selection
Non selection
DQ1~8
DQ9~16
Write
Read
Write
Read
Write
Read
BLOCK DIAGRAM
A
0
A
1
MEMORY ARRAY
262144 WORDS
x 16 BITS
A
16
A
17
S1
S2
BC1
BC2
W
CLOCK
GENERATOR
High-Z
High-Z
High-Z
High-Z
Din
Dout
High-Z
High-Z
High-Z
High-Z
Din
Dout
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Din
Dout
High-Z
Din
Dout
High-Z
Icc
Standby
Standby
Standby
Standby
Activ e
Activ e
Activ e
Activ e
Activ e
Activ e
Activ e
Activ e
Activ e
DQ
1
DQ
8
-
DQ
9
DQ
16
Vcc
GND
OE
MITSUBISHI ELECTRIC
2
revision-P04, ' 98.12.16
MITSUBISHI LSIs
M5M5V416BTP,RT
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Supply v oltage
Input v oltage
Output v oltage
Power dissipation
Operating
temperature
Storage temperature
Conditions
With respect to GND
With respect to GND
With respect to GND
Ta=25°C
Standard
W-v ersion
I-v ersion
(-L, -H)
(-LW, -HW)
(-LI, -HI)
Ratings
Units
Vcc
V
I
V
O
P
d
T
a
T
stg
-0.5
*
~ +4.6
-0.5
*
~ Vcc + 0.5
0 ~ Vcc
700
0 ~ +70
- 20 ~ +85
- 40 ~ +85
- 65 ~ +150
V
mW
°C
°C
* -3.0V in case of AC (Pulse width < 30ns)
=
DC ELECTRICAL CHARACTERISTICS
Symbol
( Vcc=2.7 ~ 3.6V, unless otherwise noted)
Conditions
Limits
Min
Ty p
Max
Vcc+0.3V
Units
Parameter
High-lev el input v oltage
Low-lev el input v oltage
High-level output voltage 1
High-level output voltage 2
V
IH
V
IL
V
OH1
V
OH2
V
OL
I
I
I
O
Icc
1
Icc
2
Low-lev el output v oltage
Input leakage current
Output leakage current
Activ e supply c urrent
( AC,MOS lev el )
Activ e supply c urrent
( AC,TTL lev el )
I
OH
= -0.5mA
I
OH
= -0.05mA
I
OL
=2mA
V
I
=0
~
Vcc
BC1 and BC2=VIH or S1=VIH or S2=VIH or OE=VIH, VI/O=0 ~ Vcc
BC1 and BC2< 0.2V, S1< 0.2V, S2 Vcc-0.2V
=
=
>
other inputs < 0.2V or = Vcc-0.2V
=
Output - open (duty 100%)
2.2
-0.3 *
2.4
Vcc-0.5V
0.6
V
0.4
±1
±1
50
10
50
10
48
24
24
12
3.6
1.2
1.2
1.2
0.5
mA
µA
f = 10MHz
f = 1MHz
f = 10MHz
f = 1MHz
+70 ~ +85°C
+70°C
+70 ~ +85°C
+40 ~ +70°C
+25 ~ +40°C
0 ~ +25°C
- 20 ~ +25°C
- 40 ~ +25°C
BC1 and BC2=V
IL
, S=V
IL
,S2=V
IH
other pins =V
IH or
V
IL
Output - open (duty 100%)
<1>
>
S1
=
Vcc - 0.2V,
-
-
-
-
-
-
-
-
-
-
-
-
-
40
5
40
5
-
-
-
-
1
0.3
0.3
0.3
-
mA
-LW, -LI
-L, -LW, -LI
-HW, -HI
-H, -HW, -HI
-H
-HW
-HI
other inputs = 0 ~ Vcc
<2>
Icc
3
Stand by s upply current
( AC,MOS lev el )
S2
<3>
0.2V,
other inputs = 0 ~ Vcc
>
BC1 and BC2
=
Vcc - 0.2V
>
S1
<
0.2V, S2
=
Vcc - 0.2V
=
Other inputs=0~Vcc
µA
Icc
4
Stand by s upply current
( AC,TTL lev el )
BC1 and BC2=V
IH
or S1=V
IH
or S2=V
IL
Other inputs= 0 ~ Vcc
Note 1: Direction for current flowing into IC is indicated as positive (no mark)
Note 2: Typical value is for Vcc=3.0V and Ta=25
°
C
* -3.0V in case of AC (Pulse width < 30ns)
=
CAPACITANCE
Symbol
Parameter
Input capacitance
Output capacitance
Conditions
(Vcc=2.7 ~ 3.6V, unless otherwise noted)
Limits
Ty p
Units
Min
Max
C
I
C
O
V
I
=GND, V
I
=25mVrms, f =1MHz
V
O
=
GND,V
O
=25mVrms, f =1MHz
10
10
pF
MITSUBISHI ELECTRIC
3
revision-P04, ' 98.12.16
MITSUBISHI LSIs
M5M5V416BTP,RT
AC ELECTRICAL CHARACTERISTICS
(1) TEST CONDITIONS
Supply v oltage
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM
(Vcc=2.7 ~ 3.6V, unless otherwise noted)
2.7V~3.6V
Input pulse
V
IH
=2.4V,V
IL
=0.4V
Input rise time and f all time
5ns
Ref erence lev el
1TTL
DQ
CL
Including scope and
jig capacitance
V
OH
=V
OL
=1.5V
Transition is measured ±500mV f rom
steady state voltage.(f or t
en
,t
dis
)
Output loads
Fig.1,CL=30pF
CL=5pF (for ten,tdis)
Limits
Fig.1 Output load
(2) READ CYCLE
Symbol
t
CR
t
a
(A)
t
a
(S1)
t
a
(S2)
t
a
(BC1)
t
a
(BC2)
t
a
(OE)
t
dis
(S1)
t
dis
(S2)
t
dis
(BC1)
t
dis
(BC2)
t
dis
(OE)
t
en
(S1)
t
en
(S2)
t
en
(BC1)
t
en
(BC2)
t
en
(OE)
t
V
(A)
Parameter
Read cy cle time
Address access time
Chip select 1 access time
Chip select 2 access time
By te control 1 access time
By te control 2 access time
Output enable access time
Output disable time af t er S1 high
Output disable time af t er S2 low
Output disable time af t er BC1 high
Output disable time af t er BC2 high
Output disable time af t er OE high
Output enable time af ter S1 low
Output enable time af ter S2 high
Output enable time af ter BC1 low
Output enable time af ter BC2 low
Output enable time af ter OE low
Data v alid time after address
70L,70H,70LW
70HW,70LI,70HI
85L,85H,85LW
85HW,85LI,85HI
10L,10H,10LW
10HW,10LI,10HI
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Min
70
Max
70
70
70
70
70
35
25
25
25
25
25
Min
85
Max
85
85
85
85
85
45
30
30
30
30
30
Min
100
Max
100
100
100
100
100
50
35
35
35
35
35
10
10
10
10
10
10
10
10
10
5
10
10
10
10
10
5
10
(3) WRITE CYCLE
Limits
Symbol
Parameter
Write cy cle time
Write pulse width
Address setup time
Address setup time with respect to W
By te control 1 setup time
By te control 2 setup time
Chip select 1 setup time
Chip select 2 setup time
Data setup time
Data hold time
Write recov ery time
Output disable time f rom W low
Output disable time f rom OE high
Output enable time f rom W high
Output enable time f rom OE low
70L,70H,70LW
85L,85H,85LW
70HW,70LI,70HI 85HW,85LI,85HI
10L,10H,10LW
10HW,10LI,10HI
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
CW
t
w
(W)
t
su
(A)
t
su
(A-WH)
t
su
(BC1)
t
su
(BC2)
t
su
(S1)
t
su
(S2)
t
su
(D)
t
h
(D)
t
rec
(W)
t
dis
(W)
t
dis
(OE)
t
en
(W)
t
en
(OE)
Min
70
55
0
65
65
65
65
65
35
0
0
Max
Min
85
60
0
70
70
70
70
70
35
0
0
Max
Min
100
75
0
85
85
85
85
85
40
0
0
Max
25
25
5
5
5
5
30
30
5
5
35
35
ns
ns
ns
ns
MITSUBISHI ELECTRIC
4
revision-P04, ' 98.12.16
MITSUBISHI LSIs
M5M5V416BTP,RT
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM
(4)TIMING DIAGRAMS
Read cycle
A
0~17
t
CR
t
a
(A)
t
a
(BC1)
or
t
v
(A)
t
a
(BC2)
(Note3)
BC1,BC2
(Note3)
t
dis
(BC1) or
t
dis
(BC1)
t
a
(S1)
S1
(Note3)
t
dis
(S1)
t
a
(S2)
(Note3)
S2
(Note3)
t
dis
(S2)
t
a
(OE)
(Note3)
OE
(Note3)
W = "H" lev el
t
en
(OE)
t
en
(BC1)
t
en
(BC2)
t
en
(S1)
t
en
(S2)
t
CW
t
dis
(OE)
(Note3)
DQ
1~16
VALID DATA
Write cycle ( W control mode )
A
0~17
t
su
(BC1) or
t
su
(BC2)
BC1,BC2
(Note3)
(Note3)
S1
(Note3)
t
su
(S1)
(Note3)
S2
(Note3)
t
su
(S2)
(Note3)
OE
t
su
(A)
W
t
dis
(OE)
DQ
1~16
t
su
(A-WH)
t
w
(W)
t
dis
(W)
t
rec
(W)
t
en
(OE)
t
en
(W)
DATA IN
STABLE
t
su
(D)
t
h
(D)
MITSUBISHI ELECTRIC
5
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