54RHST109FS datasheet, PDF - EEWORLD Datasheet

54RHST109FS: DescriptionJ-Kbar Flip-Flop, HST/T Series, 2-Func, Positive Edge Triggered, 2-Bit, Complementary Output, CMOS, CDFP16; Categorylogic logic; File Size2MB，84 Pages; ManufacturerDynex; Websitehttp://www.dynexsemi.com/

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54RHST109FS Overview

J-Kbar Flip-Flop, HST/T Series, 2-Func, Positive Edge Triggered, 2-Bit, Complementary Output, CMOS, CDFP16

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
package instruction	DFP, FL16,.3
Reach Compliance Code	unknown
Other features	RADIATION HARD CMOS/SILICON ON SAPPHIRE (SOS) TECHNOLOGY
series	HST/T
JESD-30 code	R-CDFP-F16
JESD-609 code	e0
Load capacitance (CL)	50 pF
Logic integrated circuit type	J-KBAR FLIP-FLOP
MaximumI(ol)	0.009 A
Number of digits	2
Number of functions	2
Number of terminals	16
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Output polarity	COMPLEMENTARY
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	DFP
Encapsulate equivalent code	FL16,.3
Package shape	RECTANGULAR
Package form	FLATPACK
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5 V
Prop。Delay @ Nom-Sup	25 ns
propagation delay (tpd)	25 ns
Certification status	Not Qualified
Filter level	38535V;38534K;883S
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	FLAT
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
total dose	100k Rad(Si) V
Trigger type	POSITIVE EDGE
Base Number Matches	1

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