M5M51016BTP,RT-12VL,
-12VLL
1048576-BIT(65536-WORD BY 16-BIT)CMOS STATIC RAM
1048576-BIT(65536-WORD BY 16-BIT)CMOS STATIC RAM
DESCRIPTION
The M5M51016BTP, RT are a 1048576-bit CMOS static RAM
organized as 65536 word by 16-bit which are fabricated using
high-performance triple polysilicon CMOS technology. The use of
resistive load NMOS cells and CMOS periphery result in a high
density and low power static RAM.
They are low stand-by current and low operation current and ideal
for the battery back-up application.
The M5M51016BTP,RT are packaged in a 44-pin thin small
outline package which is a high reliability and high density surface
mount device (SMD). Two types of devices are available.
M5M51016BTP(normal lead bend type package), M5M51016BRT
(reverse lead bend type package). Using both types of devices, it
becomes very easy to design a printed circuit board.
MITSUBISHI LSIs
MITSUBISHI LSIs
9 Jul ,1997
PIN CONFIGURATION (TOP VIEW)
NC
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
CHIP SELECT
INPUT
CS
1
2
3
4
5
6
7
8
44
43
42
41
40
39
38
37
NC
BC
1
BC
2
A
14
A
15
BYTE
CONTROL
INPUTS
ADDRESS
INPUTS
ADDRESS
INPUTS
9
10
11
12
13
14
15
16
17
18
19
20
21
22
36
35
34
33
32
31
30
29
28
27
26
25
24
23
FEATURES
Power supply current
Type name
Access time
(max)
Active
(max)
stand-by
(max)
60µA
(V
CC
= 3.6V)
M5M51016BTP,RT-12VL
120ns
12mA
(1MHz)
M5M51016BTP,RT-12VLL
120ns
12µA
(V
CC
= 3.6V)
0.3µA
(V
CC
= 3.0V,
typ)
Single +3.0V power supply
Low stand-by current 0.3µA (typ.)
Directly TTL compatible : All inputs and outputs
Easy memory expansion and power down by CS, BC
1
& BC
2
Data hold on +2V power supply
Three-state outputs : OR-tie capability
OE prevents data contention in the I/O bus
Common data I/O
Package
M5M51016BTP,RT .............................. 44pin 400mil TSOP(II)
(0V)GND
OUTPUT ENABLE
INPUT
OE
NC
DQ
1
DQ
2
DQ
3
DATA
DQ
4
INPUTS/
OUTPUTS
DQ
5
DQ
6
DQ
7
DQ
8
A
13
WRITE
CONTROL
W
INPUTS
A
8
A
9
ADDRESS
INPUTS
A
11
A
10
GND(0V)
NC
DQ
16
DQ
15
DQ
14
DQ
13
DATA
INPUTS/
DQ
12
OUTPUTS
DQ
11
DQ
10
DQ
9
V
CC
(5V)
Outline 44P3W - H (400mil TSOP Normal Bend)
M5M51016BTP
APPLICATION
Small capacity memory units
NC
BYTE
BC
1
CONTROL
INPUTS
BC
2
A
14
ADDRESS
INPUTS
A
15
A
13
WRITE
CONTROL
W
INPUTS
A
8
ADDRESS
A
9
INPUTS
A
11
A
10
(0V)GND
NC
DQ
16
DQ
15
DQ
14
DATA
DQ
13
INPUTS/
OUTPUTS
DQ
12
DQ
11
DQ
10
DQ
9
(5V)V
CC
44
43
42
41
40
39
38
37
1
2
3
4
5
6
7
8
36
35
34
33
32
31
30
29
28
27
26
25
24
23
9
10
11
12
13
14
15
16
17
18
19
20
21
22
NC
A
12
A
7
A
6
A
5
ADDRESS
A
4
INPUTS
A
3
A
2
A
1
A
0
CHIP SELECT
CS
INPUT
GND(0V)
OUTPUT ENABLE
OE
INPUT
NC
DQ
1
DQ
2
DQ
3
DQ
4
DATA
INPUTS/
DQ
5
OUTPUTS
DQ
6
DQ
7
DQ
8
Outline 44P3W - J (400mil TSOP Reverse Bend)
NC : NO CONNECTION
M5M51016BRT
MITSUBISHI
ELECTRIC
1
9 Jul ,1997
MITSUBISHI LSIs
M5M51016BTP,RT-12VL,
-12VLL
1048576-BIT(65536-WORD BY 16-BIT)CMOS STATIC RAM
FUNCTION
The operation mode of the M5M51016B series are determined by
a combination of the device control inputs BC
1
, BC
2
, CS, W and
OE. Each mode is summarized in the function table.
A write cycle is executed whenever the low level W overlaps with
the low level BC
1
and/or BC
2
and the high level CS. The address
must be set up before the write cycle and must be stable during
the entire cycle.
The data is latched into a cell on the trailing edge of W, BC
1
, BC
2
or CS, whichever occurs first, requiring the set-up and hold time
relative to these edge to be maintained. The output enable input
OE directly controls the output stage. Setting the OE at a high
level, the output stage is in a high-impedance state, and the
databus contention problem in the write cycle is eliminated.
A read cycle is executed by setting W at a high level and OE at a
low level while BC
1
and/or BC
2
and CS are in an active state.
(BC
1
and/or BC
2
=L,CS=H)
When setting BC
1
at a high level and the other pins are in an
active state, upper-Byte are in a selectable mode in which both
reading and writing are enabled, and lower-Byte are in a
non-selectable mode.And when setting BC
2
at a high level and the
other pins are in an active state, lower-Byte are in a selectable
mode and upper -Byte are in a non-selectable mode.
When setting BC
1
and BC
2
at a high level or CS at a low level,
the chips are in a non-selectable mode in which both reading and
writing are disabled.
In this mode, the output stage is in a high-impedance state,
allowing OR-tie with other chips and memory expansion by BC
1
,
BC
2
and CS. The power supply current is reduced as low as the
stand-by current which is specified as I
CC3
or I
CC4
, and the memory
data can be held at +2V power supply, enabling battery back-up
operation during powerfailure or power-down operation in the
non-selected mode.
DQ
1
~
8
DQ
9
~
16
I
CC
CS BC
1
BC
2
W OE
Mode
L
X X X X
Non selection
High-Z High-Z Stand-by
X
H H X X
Non selection
High-Z High-Z Stand-by
Din
Active
H
H L
L
X
Upper-Byte Write
High-Z
H
H L
H L
Upper-Byte Read
High-Z
Dout
Active
H
H L
H H
High-Z High-Z Active
H
L
H L
X
Lower-Byte Write
Din
High-Z Active
H
L
H H L
Lower-Byte Read
Dout
High-Z Active
L
H H H
High-Z High-Z Active
H
Din
Din
H
L
L
L
X Word Write
Active
H
L
L
H L Word Read Dout
Dout
Active
L
L
H H
High-Z High-Z Active
H
(High-Z=High-impedance)
BLOCK DIAGRAM
OUTPUT BUFFER
A
1
9
A3 7
A6 4
A7 3
A12 2
A14 41
A1540
A13 39
A8 37
ADDRESS
INPUTS
A9 36
SENSE AMP.
15 DQ1
16 DQ2
17 DQ3
18 DQ4
19 DQ5
20 DQ6
21 DQ7
22 DQ8
SENSE AMP.
24 DQ9
25 DQ10
26 DQ11
27 DQ12
28 DQ13
29 DQ14
30 DQ15
31 DQ16
DATA
INPUTS/
OUTPUTS
ADDRESS INPUT
BUFFER
ROW DECODER
65536 WORDS x16 BITS
( 1024 ROWS
x 256 COLUMNS
x 4 BLOCKS )
ADDRESS
INPUT
BUFFER
A4 6
A2 8
A5 5
ADDRESS
INPUT
BUFFER
BLOCK
DECODER
COLUMN
DECODER
A0 10
A10 34
A11 35
CHIP SELECT
INPUT
BYTE
CONTROL
INPUTS
CS 11
BC1 43
BC2 42
CLOCK
GENERATOR
INPUT
DATA
CONTROL
INPUT
DATA
CONTROL
OUTPUT BUFFER
23 Vcc
33 GND(0V)
12 GND (0V)
WRITE CONTROL W
38
INPUT
OUTPUT ENABLE OE 13
INPUT
MITSUBISHI
ELECTRIC
2
9 Jul ,1997
MITSUBISHI LSIs
M5M51016BTP,RT-12VL,
-12VLL
1048576-BIT(65536-WORD BY 16-BIT)CMOS STATIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Vcc
V
I
V
O
P
d
T
opr
T
stg
Parameter
Supply voltage
Input voltage
Output voltage
Power dissipation
Operating temperature
Storage temperature
Conditions
With respect to GND
Ta=25
C
o
Ratings
– 0.3 ~ 4.6
– 0.3* ~ Vcc + 0.3
0 ~ Vcc
1
0 ~ 70
– 65 ~ 150
Unit
V
V
V
o
W
C
o
C
* –3.0V in case of AC ( Pulse width
<
50ns )
DC ELECTRICAL CHARACTERISTICS
(Ta=0 ~70
C
, Vcc=2.7V ~ 3.6V, unless otherwise noted)
Symbol
V
IH
V
IL
V
OH1
V
OH2
V
OL
I
I
I
O
I
CC1W
I
CC2W
I
CC1B
I
CC2B
Parameter
High-level input voltage
Low-level input voltage
High-level output voltage 1
High-level output voltage 2
Low-level output voltage
Input current
Output current in off-state
Word operation (16bit)
Active supply current
(AC,TTL level)
Byte operation (8bit)
Active supply current
(AC,TTL level)
I
OH
= – 1mA
I
OH
= – 0.1mA
I
OL
= 2mA
V
I
=0 ~ Vcc
BC
1
and BC
2
= V
IH
or CS = V
IL
or
OE = V
IH
, V
I/O
= 0 ~ Vcc
BC
1
and BC
2
= V
IL
, CS = V
IH
other inputs = V
IH
or V
IL
Output-open(duty 100%)
(BC
1
= V
IH
and BC
2
= V
IL
)
or (BC
1
= V
IL
and BC
2
= V
IH
),
CS = V
IH
other inputs = V
IH
or V
IL
Output-open(duty 100%)
1) CS
<
0.2V, other inputs = 0
~
Vcc
2) BC
1
,BC
2
>
Vcc - 0.2V,
CS
>
Vcc - 0.2V
other inputs = 0
~
Vcc
BC
1
and BC
2
= V
IH
or CS = V
IL
,
other inputs = 0
~
Vcc
Min
cycle
1MHz
Min
cycle
1MHz
o
Test conditions
Min
2.0
– 0.3*
2.4
Vcc–0.5V
Limits
Typ
Max
Vcc+0.3V
Unit
V
V
V
V
V
µA
µA
mA
mA
mA
mA
µA
µA
mA
0.6
0.4
+
_1
+
_1
55
12
35
10
60
12
0.33
-VL
-VLL
I
CC3
Stand-by current
I
CC4
Stand-by current
* –3.0V in case of AC ( Pulse width
<
30ns )
CAPACITANCE
(Ta=0 ~ 70
C
, Vcc=2.7V ~ 3.6V, unless otherwise noted)
o
Symbol
C
I
C
IBC
C
O
Parameter
Input capacitance ( except BC
1
,BC
2
)
Input capacitance ( BC
1
,BC
2
)
Output capacitance
Test conditions
V
I
=GND, V
I
=25mVrms, f=1MHz
V
I
=GND, V
I
=25mVrms, f=1MHz
V
O
=GND,V
O
=25mVrms, f=1MHz
Min
Limits
Typ
Max
6
9
8
Unit
pF
pF
pF
Note 1: Direction for current flowing into an IC is positive (no mark).
o
2: Typical value is Vcc = 3.3V, Ta = 25 C
MITSUBISHI
ELECTRIC
3
9 Jul ,1997
MITSUBISHI LSIs
M5M51016BTP,RT-12VL,
-12VLL
1048576-BIT(65536-WORD BY 16-BIT)CMOS STATIC RAM
AC ELECTRICAL CHARACTERISTICS
(Ta = 0 ~ 70
C
, V
CC
= 2.7V ~ 3.6V, unless otherwise noted )
o
(1) MEASUREMENT CONDITIONS
Input pulse level ...................... V
IH
= 2.2V, V
IL
= 0.4V
Input rise and fall time .............. 5ns
Reference level ........................ V
OH
= 1.5V, V
OL
= 1.5V
Output loads ............................ Fig.1,C
L
= 30pF
C
L
= 5pF ( for t
en
, t
dis
)
+
Transition is measured _ 500mV from steady
state voltage. ( for t
en
, t
dis
)
1TTL
DQ
C
L
( Including scope
and JIG )
Fig.1 Output load
(2) READ CYCLE
Limits
Symbol
Parameter
M5M51016B
-12VL,-12VLL
Min
Typ
Max
120
120
120
120
120
60
40
40
40
40
10
10
10
5
10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
CR
t
a(A)
t
a(BC1)
t
a(BC2)
t
a(CS)
t
a(OE)
t
dis(BC1)
t
dis(BC2)
t
dis(CS)
t
dis(OE)
t
en(BC1)
t
en(BC2)
t
en(CS)
t
en(OE)
t
v(A)
Read cycle time
Address access time
Byte control 1 access time
Byte control 2 access time
Chip select access time
Output enable access time
Output disable time after BC
1
high
Output disable time after BC
2
high
Output disable time after CS low
Output disable time after OE high
Output enable time after BC
1
low
Output enable time after BC
2
low
Output enable time after CS high
Output enable time after OE low
Data valid time after address
(3) WRITE CYCLE
Limits
M5M51016B
-12VL,-12VLL
Max
Min
Typ
120
85
0
100
100
100
100
45
0
0
40
40
5
5
Symbol
Parameter
Unit
t
CW
t
w(W)
t
su(A)
t
su(A-WH)
t
su(BC1)
t
su(BC2 )
t
su(CS)
t
su(D)
t
h(D)
t
rec(W)
t
dis(W)
t
dis(OE)
t
en(W)
t
en(OE)
Write cycle time
Write pulse width
Address set up time
Address set up time with respect to W
Byte control 1 setup time
Byte control 2 setup time
Chip select set up time
Data set up time
Data hold time
Write recovery time
Output disable time from W low
Output disable time from OE high
Output enable time from W high
Output enable time from OE low
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MITSUBISHI
ELECTRIC
4
9 Jul ,1997
MITSUBISHI LSIs
M5M51016BTP,RT-12VL,
-12VLL
1048576-BIT(65536-WORD BY 16-BIT)CMOS STATIC RAM
(4) TIMING DIAGRAMS
Read cycle
t
CR
A
0
~
15
t
a(A)
t
a (BC1) or
t
a (BC2)
(Note 3)
(Note 3)
t
v (A)
BC
1
and/or BC
2
t
dis (BC1)
or
t
dis (BC2)
CS
(Note 3)
t
a (CS)
t
a (OE)
t
en (OE)
t
dis (CS)
(Note 3)
OE
(Note 3)
t
en (BC1)
t
en (BC2)
t
en (CS)
t
dis (OE)
(Note 3)
DQ
1
~
16
W = "H" level
DATA VALID
Write cycle (W control mode)
t
CW
A
0
~
15
t
su (BC1) or
t
su (BC2)
BC
1
and/or BC
2
(Note 3)
(Note 3)
CS
(Note 3)
t
su (CS)
(Note 3)
t
su (A-WH)
OE
t
su (A)
W
t
w (W)
t
rec (W)
t
dis (W)
t
dis (OE)
DQ
1
~
16
t
en (W)
DATA IN
STABLE
t
su (D)
t
h (D)
t
en(OE)
MITSUBISHI
ELECTRIC
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