SDRAM (Rev. 0.3)
MITSUBISHI LSIs
Feb ‘97
Preliminary
M5M4V4S40CTP-12, -15
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM
PRELIMINARY
Some of contents are described for general products
and are subject to change without notice.
DESCRIPTION
The M5M4V4S40CTP is a 2-bank x 131,072-word x 16-bit
Synchronous DRAM, with LVTTL interface. All inputs and
outputs are referenced to the rising edge of CLK. The
M5M4V4S40CTP achieves very high speed data rates up to
83MHz, and is suitable for main memory or graphic memory
in computer systems.
Vdd
DQ0
DQ1
VssQ
DQ2
DQ3
VddQ
DQ4
DQ5
VssQ
DQ6
DQ7
VddQ
DQML
/WE
/CAS
/RAS
/CS
BA
A8
A0
A1
A2
A3
Vdd
PIN CONFIGURATION
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
Vss
DQ15
DQ14
VssQ
DQ13
DQ12
VddQ
DQ11
DQ10
VssQ
DQ9
DQ8
VddQ
NC
DQMU
CLK
CKE
NC
NC
NC
A7
A6
A5
A4
Vss
FEATURES
- Single 3.3v±0.3v power supply
- Clock frequency 83MHz / 67MHz
- Fully synchronous operation referenced to clock rising edge
- Dual bank operation controlled by BA(Bank Address)
- /CAS latency- 1/2/3 (programmable)
- Burst length- 1/2/4/8/FP (programmable)
- Sequential and interleave burst (programmable)
- Byte control by DQMU and DQML
- Random column access
- Auto precharge / All bank precharge controlled by A8
- Auto and self refresh
- 1024 refresh cycles /16.4ms
CLK
- LVTTL Interface
CKE
- 400-mil, 50-pin Thin Small Outline Package
/CS
(TSOP II) with 0.8mm lead pitch
/RAS
Max.
Frequency
M5M4V4S40CTP-12
M5M4V4S40CTP-15
83MHz
67MHz
CLK Access
Time
8ns
9ns
/CAS
/WE
DQ0-15
DQMU
DQML
A0-8
BA
Vdd
VddQ
Vss
VssQ
: Master Clock
: Clock Enable
: Chip Select
: Row Address Strobe
: Column Address Strobe
: Write Enable
: Data I/O
: Upper Output Disable/ Write Mask
: Lower Output Disable/ Write Mask
: Address Input
: Bank Address
: Power Supply
: Power Supply for Output
: Ground
: Ground for Output
400mil 50pin TSOP(II)
MITSUBISHI ELECTRIC
1
SDRAM (Rev. 0.3)
MITSUBISHI LSIs
Feb ‘97
Preliminary
M5M4V4S40CTP-12, -15
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM
BLOCK DIAGRAM
DQ0-15
I/O Buffer
Memory Array
Bank #0
Memory Array
Bank #1
Mode
Register
Control Circuitry
Address Buffer
Clock Buffer
Control Signal Buffer
A0-8
BA
/CS /RAS /CAS /WE
DQML DQMU
CLK
CKE
Type Designation Code
These rules are only applied to the Synchronous DRAM family.
M 5M 4 V 4 S 4 0 C TP - 12
Cycle Time (min.) 12: 12ns, 15: 15ns
Package Type TP: TSOP(II)
Process Generation
Function 0: Random Column, 1: 2N-rule
Organization 2 n 4: x16
Synchronous DRAM
Density 4:4M bits
Interface V:LVTTL
Memory Style (DRAM)
Use, Recommended Operating Conditions, etc
Mitsubishi Main Designation
MITSUBISHI ELECTRIC
2
SDRAM (Rev. 0.3)
MITSUBISHI LSIs
Feb ‘97
Preliminary
M5M4V4S40CTP-12, -15
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM
PIN FUNCTION
CLK
Input
Master Clock: All other inputs are referenced to the rising edge of CLK.
Clock Enable: CKE controls the internal clock. When CKE is low, the
internal clock for the following cycle is disabled. CKE is also used to select
auto and self refresh. After self-refresh mode is started, CKE acts as an
asynchronous input to maintain and exit the mode.
Chip Select: When /CS is high, all commands are inhibited.
/RAS, /CAS, and /WE are used to define basic commands.
A0-8 specify the Row and Column addresses within the selected bank.
The Row Address is set by A0-8 and the Column Address is set by A0-7.
A8 is also used to indicate the precharge option. When A8 is high during
read or write command, an auto precharge is performed. When A8 is
high during a precharge command, both banks are precharged.
Bank Address: BA is not simply A9. BA specifies the bank to which a
command is applied. BA must be set during the ACT, PRE, READ,
and WRITE commands.
Data In and data out are referenced to the rising edge of CLK.
Lower Din(0-7) Mask; Lower Dout(0-7) Disable; When DQML is high
during burst write Din(0-7) for the current cycle is masked. When DQML
is high during burst read Dout(0-7) is disabled two cycles later.
Upper Din(8-15) Mask; Upper Dout(8-15) Disable; When DQMU is high
during burst write Din(8-15) for the current cycle is masked. When DQMU
is high during burst read Dout(8-15) is disabled two cycles later.
Power Supply for the memory array and peripheral circuitry.
Power Supply for the output buffers only.
CKE
Input
/CS
/RAS, /CAS, /WE
Input
Input
A0-8
Input
BA
Input
DQ0-15
Input / Output
DQML
Input
DQMU
Input
Vdd, Vss
VddQ, VssQ
Power Supply
Power Supply
MITSUBISHI ELECTRIC
3
SDRAM (Rev. 0.3)
MITSUBISHI LSIs
Feb ‘97
Preliminary
M5M4V4S40CTP-12, -15
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM
BASIC FUNCTIONS
The M5M4V4S40CTP has the following basic functions, bank (row) activate, burst read/write, bank
(row) precharge, and auto/self refresh. Each command is defined by the control signals (/RAS, /CAS and
/WE) at the rising edge of CLK. The inputs /CS ,CKE and A8 are used for chip select, refresh options, and
precharge options, respectively.
Please see the command truth table for detailed definitions.
CLK
/CS
/RAS
/CAS
/WE
CKE
A8
Chip Select : L=select, H=deselect
Command
Command
Command
Refresh Option @refresh command
Precharge Option @precharge or read/write command
define basic commands
Activate (ACT) [/RAS =L, /CAS =/WE =H]
The ACT command activates a row in an idle bank. The bank address, BA, is used to select which of
the two banks will be activated.
Read (READ) [/RAS =H, /CAS =L, /WE =H]
The READ command starts burst read from the active bank indicated by BA. The first output data
appears after /CAS latency. If A8 =H when READ is issued the bank is automatically precharged after
the last burst read (READA).
Note: READA is not valid for FP burst operations.
Write (WRITE) [/RAS =H, /CAS =/WE =L]
The WRITE command starts burst write to the active bank indicated by BA. Total data length to be
written is set by burst length. If A8 =H when WRITE is issued the bank is automatically precharged
after the last burst write (WRITEA).
Note: WRITEA is not valid for FP burst operations.
Precharge (PRE) [/RAS =L, /CAS =H, /WE =L]
The PRE command deactivates the active bank indicated by BA. This command also terminates burst
read and write operations. If A8 =H when PRE is issued both banks are automatically precharged (PREA).
Auto-Refresh (REFA) [/RAS =/CAS =L, /WE =CKE =H]
The REFA command starts an auto-refresh cycle. The refresh address, including the bank address, is
generated internally. After this command, the banks are precharged automatically.
MITSUBISHI ELECTRIC
4
SDRAM (Rev. 0.3)
MITSUBISHI LSIs
Feb ‘97
Preliminary
M5M4V4S40CTP-12, -15
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM
COMMAND TRUTH TABLE
COMMAND
Deselect
No Operation
Row Address Entry &
Bank Activate
Single Bank Precharge
Precharge All Banks
Column Address Entry
& Write
Column Address Entry
& Write with Auto-
Precharge
Column Address Entry
& Read
Column Address Entry
& Read with Auto-
Precharge
Auto-Refresh
Self-Refresh Entry
Self-Refresh Exit
Burst Terminate
Mode Register Set
MNEMONIC
DESEL
NOP
ACT
PRE
PREA
WRITE
CKE
n-1
H
H
H
H
H
H
CKE
n
X
X
X
X
X
X
/CS
H
L
L
L
L
L
/RAS
X
H
L
L
L
H
/CAS
X
H
H
H
H
L
/WE
X
H
H
L
L
L
BA
X
X
V
V
X
V
A8
X
X
V
L
H
L
A0-7
X
X
V
X
X
V
WRITEA
H
X
L
H
L
L
V
H
V
READ
H
X
L
H
L
H
V
L
V
READA
REFA
REFS
REFSX
TBST
MRS
H
H
H
L
L
H
H
X
H
L
H
H
X
X
L
L
L
H
L
L
L
H
L
L
X
H
H
L
L
L
L
X
H
H
L
H
H
H
X
H
L
L
V
X
X
X
X
X
V
H
X
X
X
X
X
L
V
X
X
X
X
X
V*1
H=High Level, L=Low Level, V=Valid, X=Don’t Care, n=CLK cycle number
NOTE:
1. A7 =0, A0-A6 =Mode Address
MITSUBISHI ELECTRIC
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