(Rev. 1.1)
MITSUBISHI LSIs
M5M467400/465400BJ,BTP -5,-6,-5S,-6S
M5M467800/465800BJ,BTP -5,-6,-5S,-6S
M5M465160BJ,BTP -5,-6,-5S,-6S
FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
DESCRIPTION
The M5M467400/465400BJ,BTP is organized 16777216-word by 4-bit, M5M467800/465800BJ,BTP is organized 8388608-word by
8-bit, and M5M465160BJ,BTP is organized 4194304-word by 16-bit dynamic RAMs, fabricated with the high performance CMOS
process, and are suitable for large-capacity memory systems with high speed and low power dissipation.
The use of double-layer aluminum process combined with CMOS technology and a single-transistor dynamic storage stacked
capacitor cell provide high circuit density. Multiplexed address inputs permit both a reduction in pins and an increase in system
densities.
FEATURES
Type name
M5M467400BXX-5,5S
M5M467800BXX-5,5S
M5M467400BXX-6,6S
M5M467800BXX-6,6S
M5M465400BXX-5,5S
M5M465800BXX-5,5S
M5M465400BXX-6,6S
M5M465800BXX-6,6S
Address
Power
RAS
OE
CAS
Cycle
access access access
access
dissipa-
time
tion
time
time
time
time
(max.ns) (max.ns) (max.ns) (max.ns) (min.ns) (typ.mW)
Type name
M5M465160BXX-5,5S
M5M465160BXX-6,6S
Power
Address
RAS
CAS
OE
Cycle
dissipa-
access access access
access
time
time
tion
time
time
time
(max.ns) (max.ns) (max.ns) (max.ns) (min.ns) (typ.mW)
50
60
50
60
13
15
13
15
25
30
25
30
13
15
13
15
90
110
90
110
300
250
390
325
50
60
13
15
25
30
13
15
90
110
420
390
XX=J,TP
Standard 32 pin SOJ, 32 pin TSOP (M5M467400Bxx/M5M465400Bxx/M5M467800Bxx/M5M465800Bxx)
Standard 50 pin SOJ, 50 pin TSOP (M5M465160Bxx)
Single 3.3
±
0.3V supply
Low stand-by power dissipation
1.8mW (Max)
LVCMOS input level
Low operating power dissipation
M5M467400Bxx-5,5S / M5M467800Bxx-5,5S
360.0mW (Max)
M5M467400Bxx-6,6S / M5M467800Bxx-6,6S
324.0mW (Max)
M5M465400Bxx-5,5S / M5M465800Bxx-5,5S
468.0mW (Max)
M5M465400Bxx-6,6S / M5M465800Bxx-6,6S
432.0mW (Max)
M5M465160Bxx-5,5S
504.0mW (Max)
M5M465160Bxx-6,6S
468.0mW (Max)
Self refresh capability*
Self refresh current
400µA (Max)
Fast-page mode , Read-modify-write, CAS before RAS refresh, Hidden refresh capabilities
Early-write mode and OE to control output buffer impedance
All inputs, outputs LVTTL compatible and low capacitance
*
:Applicable to self refresh version(M5M467400/465400/467800/465800/465160BJ,BTP-5S,-6S:option) only
ADDRESS
Part No.
Row Add Col Add
Refresh
Refresh Cycle
Normal
S-version
RAS Only Ref,Normal R/W 8192/64ms 8192/128ms
M5M467400Bxx A0-A12 A0-A10
CBR Ref,Hidden Ref
4096/64ms 4096/128ms
M5M465400Bxx A0-A11 A0-A11
RAS Only Ref,Normal R/W 4096/64ms 4096/128ms
CBR Ref,Hidden Ref
RAS Only Ref,Normal R/W 8192/64ms 8192/128ms
M5M467800Bxx A0-A12 A0-A9
CBR Ref,Hidden Ref
4096/64ms 4096/128ms
M5M465800Bxx A0-A11 A0-A10
RAS Only Ref,Normal R/W 4096/64ms 4096/128ms
CBR Ref,Hidden Ref
M5M465160Bxx A0-A11 A0-A9
RAS Only Ref,Normal R/W
4096/64ms 4096/128ms
CBR Ref,Hidden Ref
APPLICATION
Main memory unit for computers, Microcomputer memory, Refresh memory for CRT
1
MITSUBISHI
ELECTRIC
Jun. 1999
(Rev. 1.1)
MITSUBISHI LSIs
M5M467400/465400BJ,BTP -5,-6,-5S,-6S
M5M467800/465800BJ,BTP -5,-6,-5S,-6S
M5M465160BJ,BTP -5,-6,-5S,-6S
FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
PIN DESCRIPTION
M5M467400Bxx / M5M465400Bxx
Pin Name
A
0
-A
12
DQ1-DQ4
RAS
CAS
W
OE
Vcc
Vss
NC
Function
Address Inputs
Data Inputs / Outputs
Row Address Strobe Input
Column Address Strobe Input
Write Control Input
Output Enable Input
Power Supply (+3.3V)
Ground (0V)
No Connection
M5M467800Bxx / M5M465800Bxx
Pin Name
A
0
-A
12
DQ1-DQ8
RAS
CAS
W
OE
Vcc
Vss
NC
Function
Address Inputs
Data Inputs / Outputs
Row Address Strobe Input
Column Address Strobe Input
Write Control Input
Output Enable Input
Power Supply (+3.3V)
Ground (0V)
No Connection
M5M465160Bxx
Pin Name
A
0
-A
11
Function
Address Inputs
DQ1-DQ16 Data Inputs / Outputs
Row Address Strobe Input
RAS
Upper byte control
UCAS
Column Address Strobe Input
Lower byte control
LCAS
Column Address Strobe Input
Write Control Input
W
OE
Vcc
Vss
NC
Output Enable Input
Power Supply (+3.3V)
Ground (0V)
No Connection
XX=BJ,BTP
M5M467400/465400BJ,BTP
PIN CONFIGURATION (TOP VIEW)
Vcc
DQ
1
DQ
2
NC
NC
NC
NC
W
RAS
A
0
A
1
A
2
A
3
A
4
A
5
Vcc
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Vss
DQ
4
DQ
3
NC
NC
NC
CAS
OE
A
12
/NC(Note)
A
11
A
10
A
9
A
8
A
7
A
6
Vss
Vcc
DQ
1
DQ
2
NC
NC
NC
NC
W
RAS
A
0
A
1
A
2
A
3
A
4
A
5
Vcc
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Vss
DQ
4
DQ
3
NC
NC
NC
CAS
OE
A
12
/NC(Note)
A
11
A
10
A
9
A
8
A
7
A
6
Vss
Outline 32P0N (400mil SOJ)
M5M465400BJ
M5M467400BJ
Outline 32P3N (400mil TSOP Normal Bend)
Note : A12...M5M467400Bxx, NC...M5M465400Bxx
: NO CONNECTION
NC
M5M465400BTP
M5M467400BTP
2
MITSUBISHI
ELECTRIC
Jun. 1999
(Rev. 1.1)
MITSUBISHI LSIs
M5M467400/465400BJ,BTP -5,-6,-5S,-6S
M5M467800/465800BJ,BTP -5,-6,-5S,-6S
M5M465160BJ,BTP -5,-6,-5S,-6S
FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
M5M467800/465800BJ,BTP
Vcc
DQ
1
DQ
2
DQ
3
DQ
4
NC
Vcc
W
RAS
A
0
A
1
A
2
A
3
A
4
A
5
Vcc
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
PIN CONFIGURATION (TOP VIEW)
Vss
DQ
8
DQ
7
DQ
6
DQ
5
Vss
CAS
OE
A
12
/NC(Note)
A
11
A
10
A
9
A
8
A
7
A
6
Vss
Vcc
DQ
1
DQ
2
DQ
3
DQ
4
NC
Vcc
W
RAS
A
0
A
1
A
2
A
3
A
4
A
5
Vcc
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Vss
DQ
8
DQ
7
DQ
6
DQ
5
Vss
CAS
OE
A
12
/NC(Note)
A
11
A
10
A
9
A
8
A
7
A
6
Vss
Outline 32P0N (400mil SOJ)
M5M465160BJ,BTP
Vcc
DQ
1
DQ
2
DQ
3
DQ
4
Vcc
DQ
5
DQ
6
DQ
7
DQ
8
NC
Vcc
W
RAS
NC
NC
NC
NC
A
0
A
1
A
2
A
3
A
4
A
5
Vcc
1
2
3
4
5
6
7
8
9
10
50
49
48
47
46
45
44
43
42
41
M5M465800BJ
11
12 12
13
14
15
16
17
18
19
20
21
22
23
24
25
Outline 50P0G (400mil SOJ)
M5M467800BJ
M5M465160BJ
Outline 32P3N (400mil TSOP Normal Bend)
Note : A12...M5M467800Bxx, NC...M5M465800Bxx
: NO CONNECTION
NC
PIN CONFIGURATION (TOP VIEW)
Vss
DQ
16
DQ
15
DQ
14
DQ
13
Vss
DQ
12
DQ
11
DQ
10
DQ
9
NC
Vss
LCAS
UCAS
OE
NC
NC
NC
A
11
A
10
A
9
A
8
A
7
A
6
Vss
Vcc
DQ
1
DQ
2
DQ
3
DQ
4
Vcc
DQ
5
DQ
6
DQ
7
DQ
8
NC
Vcc
W
RAS
NC
NC
NC
NC
A
0
A
1
A
2
A
3
A
4
A
5
Vcc
1
2
3
4
5
6
7
8
9
10
11
12 12
13
14
15
16
17
18
19
20
21
22
23
24
25
50
49
48
47
46
45
44
43
42
41
M5M465800BTP
M5M465160BTP
M5M467800BTP
Vss
DQ
16
DQ
15
DQ
14
DQ
13
Vss
DQ
12
DQ
11
DQ
10
DQ
9
NC
Vss
LCAS
UCAS
OE
NC
NC
NC
A
11
A
10
A
9
A
8
A
7
A
6
Vss
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
Outline 50P3G (400mil TSOP Normal Bend)
NC : NO CONNECTION
3
MITSUBISHI
ELECTRIC
Jun. 1999
(Rev. 1.1)
MITSUBISHI LSIs
M5M467400/465400BJ,BTP -5,-6,-5S,-6S
M5M467800/465800BJ,BTP -5,-6,-5S,-6S
M5M465160BJ,BTP -5,-6,-5S,-6S
FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
FUNCTION
The M5M467400(800)/465400(800,160)BJ, BTP provide, in addition to normal read, write, and read-modify-write operations,
a number of other functions, e.g., Fast page mode, CAS before RAS refresh, and delayed-write.
The input conditions for each are shown in Table 1.
Table 1 Input conditions for each mode
M5M467400Bxx / M5M465400Bxx / M5M467800Bxx / M5M465800Bxx
Inputs
Operation
RAS
Read
Write (Early write)
Write (Delayed write)
Read-modify-write
RAS-only refresh
Hidden refresh
CAS before RAS refresh
Standby
ACT
ACT
ACT
ACT
ACT
ACT
ACT
NAC
CAS
ACT
ACT
ACT
ACT
NAC
ACT
ACT
DNC
W
NAC
ACT
ACT
ACT
DNC
DNC
NAC
DNC
OE
ACT
DNC
DNC
ACT
DNC
ACT
DNC
DNC
Row
address
APD
APD
APD
APD
APD
DNC
DNC
DNC
Column
address
APD
APD
APD
APD
DNC
DNC
DNC
DNC
Input/Output
Refresh
Input
OPN
VLD
VLD
VLD
OPN
OPN
DNC
DNC
Output
VLD
OPN
IVD
VLD
OPN
VLD
OPN
OPN
NO
NO
NO
NO
YES
YES
YES
NO
FAST PAGE
mode
identical
Remark
M5M465160Bxx
Inputs
Operation
RAS
Lower byte read
Upper byte read
Word read
Lower byte write
Upper byte write
Word write
RAS-only refresh
Hidden refresh
CAS before RAS refresh
Stand-by
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
NAC
LCAS
ACT
NAC
ACT
ACT
NAC
ACT
NAC
ACT
ACT
DNC
UCAS
NAC
ACT
ACT
NAC
ACT
ACT
NAC
ACT
ACT
DNC
W
NAC
NAC
NAC
ACT
ACT
ACT
DNC
NAC
DNC
DNC
OE
ACT
ACT
ACT
NAC
NAC
NAC
DNC
ACT
DNC
DNC
Row
address
APD
APD
APD
APD
APD
APD
APD
DNC
DNC
DNC
Column
address
APD
APD
APD
APD
APD
APD
DNC
DNC
DNC
DNC
Input/Output
DQ1~DQ8
VLD
OPN
VLD
DIN
DNC
DIN
OPN
VLD
OPN
OPN
DQ9~DQ16
OPN
VLD
VLD
DNC
DIN
DIN
OPN
VLD
OPN
OPN
Refresh
NO
NO
NO
NO
NO
NO
YES
YES
YES
NO
FAST PAGE
mode
identical
Remark
Note : ACT : active, NAC : nonactive, DNC : don' t care, VLD : valid, IVD : Invalid, APD : applied, OPN : open
4
MITSUBISHI
ELECTRIC
Jun. 1999
(Rev. 1.1)
MITSUBISHI LSIs
M5M467400/465400BJ,BTP -5,-6,-5S,-6S
M5M467800/465800BJ,BTP -5,-6,-5S,-6S
M5M465160BJ,BTP -5,-6,-5S,-6S
FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
M5M467400Bxx / M5M465400Bxx
BLOCK DIAGRAM
COLUMN ADDRESS
STROBE INPUT
ROW ADDRESS
STROBE INPUT
WRITE CONTROL
INPUT
Vcc (3.3V)
CAS
RAS
CLOCK GENERATOR
CIRCUIT
Vss (0V)
W
(4)
DATA IN
BUFFERS
A0~A11
(Note)
A0
A1
A2
ROW & COLUMN
ADDRESS BUFFER
A3
A4
A5
ADDRESS INPUTS
A6
A7
A8
A9
A10
A11
A12
(Note)
Note
COLUMN DECODER
SENSE REFRESH
AMPLIFIER & I /O CONTROL
ROW DECODER
DQ1
DQ2
DQ3
(4)
DATA OUT
BUFFERS
DQ4
DATA
INPUTS / OUTPUTS
A0~
A12
(Note)
MEMORY CELL
(67108864 BITS)
OE OUTPUT ENABLE
INPUT
:
Refer to Page 1 (ADDRESS)
M5M467800Bxx / M5M465800Bxx
BLOCK DIAGRAM
COLUMN ADDRESS
STROBE INPUT
ROW ADDRESS
STROBE INPUT
WRITE CONTROL
INPUT
Vcc (3.3V)
CAS
RAS
CLOCK GENERATOR
CIRCUIT
Vss (0V)
W
(8)
DATA IN
BUFFERS
A0~A10
A0
A1
A2
ROW & COLUMN
ADDRESS BUFFER
A3
A4
A5
SENSE REFRESH
AMPLIFIER & I /O CONTROL
ROW DECODER
(Note)
COLUMN DECODER
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DATA
INPUTS / OUTPUTS
A6
A7
A8
A9
A10
A11
A12
(Note)
A0~
A12
(Note)
MEMORY CELL
(67108864 BITS)
(8)
DATA OUT
BUFFERS
ADDRESS INPUTS
OE OUTPUT ENABLE
INPUT
Note
:
Refer to Page 1 (ADDRESS)
5
MITSUBISHI
ELECTRIC
Jun. 1999
京公网安备 11010802033920号
EEWORLD
