M5LV-256/192-20YC datasheet, PDF

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M5LV-256/192-20YC: DescriptionEE PLD, 7.5 ns, PQFP100; Categorysemiconductor Programmable logic devices; File Size536KB，47 Pages; ManufacturerLattice; Websitehttp://www.latticesemi.com

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M5LV-256/192-20YC Overview

EE PLD, 7.5 ns, PQFP100

M5LV-256/192-20YC Parametric

Parameter Name	Attribute value
Number of input and output buses	74
Number of terminals	100
Minimum operating temperature	0.0 Cel
Maximum operating temperature	70 Cel
state	Transferred
Programmable logic type	EE PLD
clock_frequency_max	71.4 MHz
in_system_programmable	YES
jesd_30_code	S-PQFP-G100
jtag_bs	YES
Dedicated input quantity	0.0
umber_of_macro_cells	128
organize	0 DEDICATED INPUTS, 74 I/O
Output function	MACROCELL
Packaging Materials	PLASTIC/EPOXY
ckage_code	QFP
ckage_equivalence_code	QFP100,.63SQ,20
packaging shape	SQUARE
Package Size	FLATPACK
wer_supplies	3.3
gation_delay	7.5 ns
qualification_status	COMMERCIAL
sub_category	Programmable Logic Devices
Rated supply voltage	3.3 V
Minimum supply voltage	3 V
Maximum supply voltage	3.6 V
surface mount	YES
Craftsmanship	CMOS
Temperature level	COMMERCIAL
Terminal form	GULL WING
Terminal spacing	0.5000 mm
Terminal location	QUAD
dditional_feature	128 MACROCELLS

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MACH 5 CPLD Family

Fifth Generation MACH Architecture

FEATURES

High logic densities and I/Os for increased logic integration

— 128 to 512 macrocell densities

— 68 to 256 I/Os

Wide selection of density and I/O combinations to support most application needs

— 6 macrocell density options

— 7 I/O options

— Up to 4 I/O options per macrocell density

— Up to 5 density & I/O options for each package

Performance features to ﬁt system needs

— 5.5 ns t

Commercial, 7.5 ns t

Industrial

— 182 MHz f

CNT

— Four programmable power/speed settings per block

Flexible architecture facilitates logic design

— Multiple levels of switch matrices allow for performance-based routing

— 100% routability and pin-out retention

— Synchronous and asynchronous clocking, including dual-edge clocking

— Asynchronous product- or sum-term set or reset

— 16 to 64 output enables

— Functions of up to 32 product terms

Advanced capabilities for easy system integration

— 3.3-V & 5-V JEDEC-compliant operations

— IEEE 1149.1 compliant for boundary scan testing

— 3.3-V & 5-V in-system programmable via IEEE 1149.1 Boundary Scan Test Access Por

— PCI compliant (-5/-6/-7/-10/-12 speed grades)

— Safe for mixed supply voltage system design

— Bus-Friendly™ Inputs & I/Os

— Individual output slew rate control

— Hot socketing

— Programmable security bit

Advanced E

CMOS process provides high performance, cost effective solutions

Supported by ispDesignEXPERT™ software for rapid logic development

— Supports HDL design methodologies with results optimized for MACH 5 devices

— Flexibility to adapt to user requirements

— Software partnerships that ensure customer success

Lattice and Third-party hardware programming support

— LatticePRO™ software for in-system programmability support on PCs and Automat

Equipment

— Programming support on all major programmers including Data I/O, BP Microsystem

and System General

Publication#

20446

Amendment/

Rev:

Issue Date:

September 2000

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