ICS557-01
PCI-E
XPRESS
C
LOCK
S
OURCE
Description
The ICS557-01 is a clock chip designed for use in
PCI-Express Cards as a clock source. It provides a pair
of differential outputs at 100 MHz in a small 8-pin SOIC
package.
Using ICS’ patented Phase-Locked Loop (PLL)
techniques, the device takes a 25 MHz crystal input
and produces HCSL (Host Clock Signal Level)
differential outputs at 100 MHz clock frequency. LVDS
signal levels can also be supported via an alternative
termination scheme.
Features
•
Supports PCI-Express
TM
HCSL Outputs
0.7 V current mode differential pair
•
•
•
•
•
•
•
•
•
Supports LVDS Output Levels
Packaged in 8-pin SOIC
Available in Pb (lead) free package
Operating voltage of 3.3 V
Low power consumption
Input frequency of 25 MHz
Short term jitter 100 ps (peak-to-peak)
Output Enable via pin selection
Industrial temperature range available
Block Diagram
VDD
Phase Lock
Loop
X1
25 MHz
crystal /clock
X2
Clock
Buffer/
Crystal
Oscillator
CLK
CLK
Crystal Tuning Capacitors
GND
OE
R
R
(IREF)
MDS 557-01 F
I n t e gra te d C i r c u i t S y s t e m s
●
1
525 Race Stre et, San Jo se, CA 9 5126
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Revision 011606
te l (40 8) 2 97-12 01
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w w w. i c st . c o m
ICS557-01
PCI-E
XPRESS
C
LOCK
S
OURCE
Pin Assignment
OE
X1
X2
GN D
1
2
3
4
8
7
6
5
V DD
CL K
CL K
I RE F
8 P i n ( 1 5 0 mi l ) S OI C
Pin Descriptions
Pin
Number
1
Pin
Name
OE
Pin
Type
Input
Pin Description
Output Enable signal
(H = outputs are enabled, L = outputs are disabled/tristated).
Internal pull-up resistor.
Crystal or clock input. Connect to a 25 MHz crystal or single ended clock.
Crystal Connection. Connect to a parallel mode crystal.
Leave floating if clock input.
Connect to ground.
2
3
4
5
6
7
8
X1
X2
GND
IREF
Input
XO
Power
Output A 475Ω precision resistor connected between this pin and ground
establishes the external reference current.
Output HCSL differential complementary clock output.
Output HCSL differential clock output.
Power
Connect to +3.3 V.
CLK
CLK
VDD
MDS 557-01 F
In te grated Circuit Systems
●
2
525 Ra ce Street, San Jose, CA 9512 6
●
Revision 011606
tel (4 08) 297-1 201
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w w w. i c s t . c o m
ICS557-01
PCI-E
XPRESS
C
LOCK
S
OURCE
Applications Information
External Components
A minimum number of external components are
required for proper operation.
Output Structures
IREF
=2.3 mA
6*IREF
Decoupling Capacitors
Decoupling capacitors of 0.01
µF
should be connected
between VDD and the ground plane (pin 4) as close to
the VDD pin as possible. Do not share ground vias
between components. Route power from power source
through the capacitor pad and then into ICS pin.
Crystal
A 25 MHz fundamental mode parallel resonant crystal
with C
L
= 16 pF should be used. This crystal must have
less than 300 ppm of error across temperature in order
for the ICS557-01 to meet PCI Express specifications.
R
R
475
Ω
See Output Termination
Sections - Pages 3 ~ 5
Crystal Capacitors
Crystal capacitors are connected from pins X1 to
ground and X2 to ground to optimize the accuracy of
the output frequency.
C
L
= Crystal’s load capacitance in pF
Crystal Capacitors (pF) = (C
L
- 8) * 2
For example, for a crystal with a 16 pF load cap, each
external crystal cap would be 16 pF. (16-8)*2=16.
General PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
1. Each 0.01µF decoupling capacitor should be
mounted on the component side of the board as close
to the VDD pin as possible.
2. No vias should be used between decoupling
capacitor and VDD pin.
3. The PCB trace to VDD pin should be kept as short
as possible, as should the PCB trace to the ground via.
Distance of the ferrite bead and bulk decoupling from
the device is less critical.
4. An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers (any ferrite beads and bulk decoupling
capacitors can be mounted on the back). Other signal
traces should be routed away from the ICS557-01.This
includes signal traces just underneath the device, or on
layers adjacent to the ground plane layer used by the
device.
Current Source (Iref) Reference Resistor - R
R
If board target trace impedance (Z) is 50Ω, then R
R
=
475Ω (1%), providing IREF of 2.32 mA. The output
current (I
OH
) is equal to 6*IREF.
Output Termination
The PCI-Express differential clock outputs of the
ICS557-01 are open source drivers and require an
external series resistor and a resistor to ground. These
resistor values and their allowable locations are shown
in detail in the
PCI-Express Layout Guidelines
section.
The ICS557-01can also be configured for LVDS
compatible voltage levels. See the
LVDS Compatible
Layout Guidelines
section
MDS 557-01 F
In te grated Circuit Systems
●
3
525 Ra ce Street, San Jose, CA 9512 6
●
Revision 011606
tel (4 08) 297-1 201
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w w w. i c s t . c o m
ICS557-01
PCI-E
XPRESS
C
LOCK
S
OURCE
PCI-Express Layout Guidelines
Recommendations for Differential Routing
as non-coupled 50 ohm trace.
as non-coupled 50 ohm trace.
as non-coupled 50 ohm trace.
Dimension
0.5
0.2
0.2
3
49
Dimension
2 min to
1.8 min to
Dimension
0.25 to
0.225 min t
ferential Routing on a Single PCB
as coupled
microstrip
100 ohm differential trace.
as coupled
stripline
100 ohm differential trace.
ial Routing to a PCI Express Connector
as coupled
microstrip
100 ohm differential trace.
as coupled
stripline
100 ohm differential trace.
Figure 1: PCI-Express Device Routing
L1
R
S
L1’
R
S
L2
L2’
R
T
L3’
R
T
L3
L4
L4’
ICS557-01
Output
Clock
PCI-Express
Load or
Connector
Typical PCI-Express (HCSL)
Waveform
700 mV
0
t
OR
0.52 V
0.175 V
500 ps
500 ps
t
OF
0.52 V
0.175 V
MDS 557-01 F
In te grated Circuit Systems
●
4
525 Ra ce Street, San Jose, CA 9512 6
●
Revision 011606
tel (4 08) 297-1 201
●
w w w. i c s t . c o m
ICS557-01
PCI-E
XPRESS
C
LOCK
S
OURCE
LVDS Compatible Layout Guidelines
LVDS Recommendations for Differential Routing
L1 length, Route as non-coupled 50 ohm trace.
L2 length, Route as non-coupled 50 ohm trace.
R
P
R
Q
R
T
L3 length, Route as coupled 50 ohm differential trace.
L3 length, Route as coupled 50 ohm differential trace.
Dimension or Value
0.5 max
0.2 max
100
100
150
Unit
inch
inch
ohm
ohm
ohm
Figure 3: LVDS Device Routing
L1
R
Q
L1’
L3
L3’
R
P
R
T
ICS557-01
Clock
Output
L2’
L2
R
T
LVDS
Device
Load
Typical LVDS Waveform
1325 mV
1000 mV
t
OR
500 ps
500 ps
t
OF
1250 mV
1150 mV
1250 mV
1150 mV
MDS 557-01 F
In te grated Circuit Systems
●
5
525 Ra ce Street, San Jose, CA 9512 6
●
Revision 011606
tel (4 08) 297-1 201
●
w w w. i c s t . c o m
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