KS24L321/641
32K/64K-bit
Serial EEPROM
Data Sheet
OVERVIEW
The KS24L321/641 serial EEPROM has a 32/64 Kbits (4,096/8,192 bytes) capacity, supporting the standard
I
2
C™-bus serial interface. It is fabricated using Samsung’ most advanced CMOS technology. One of its major
s
features is a hardware-based write protection circuit for the entire memory area. Hardware-based write protection
is controlled by the state of the write-protect (WP) pin. Using one-page write mode, you can load up to 32 bytes
of data into the EEPROM in a single write operation. Another significant feature of the KS24L321/641 is its
support for fast mode and standard mode.
FEATURES
I
2
C-Bus Interface
•
•
Two-wire serial interface
Automatic word address increment
Operating Characteristics
•
•
Operating voltage: 2.0 V to 5.5 V
Operating current
— Maximum write current: < 3 mA at 5.5 V
EEPROM
•
•
•
•
•
•
•
32/64 Kbits (4,096/8,192 bytes) storage area
32-byte page buffer
Typical 3-millisecond write cycle time with auto-
erase function
Hardware-based write protection for the entire
EEPROM (using the WP pin)
EEPROM programming voltage generated
on chip
1,000,000 erase/write cycles
100 years data retention
•
•
— Maximum read current: < 500
µA
at 5.5 V
— Maximum stand-by current: < 2
µA
at 2.0 V
Operating temperature range:
— – 25 °C to + 70 °C (Commercial)
— – 40 °C to + 85 °C (Industrial)
•
Operating clock frequencies
— 100 kHz at standard mode
— 400 kHz at fast mode
Electrostatic discharge (ESD)
— 5,000 V (HBM)
— 500 V (MM)
Packages
•
8-pin DIP and SOP
7-1
KS24L321/641 SERIAL EEPROM
DATA SHEET
SDA
Start/Stop
Logic
HV Generation
Timing Control
WP
Control Logic
SCL
Slave Address
Comparator
Word Address
Pointer
Row
Decoder
EEPROM
Cell Array
4,096 x 8 Bits
8,192 x 8 Bits
A0
A1
A2
Column Decoder
Data Register
D
OUT
and ACK
Figure 7-1. KS24L321/641 Block Diagram
7-2
DATA SHEET
KS24L321/641 SERIAL EEPROM
V
CC
WP
SCL
SDA
KS24L321/641
A0
A1
A2
V
SS
NOTE:
The KS24L321/641 is available in 8-pin DIP and SOP package.
Figure 7-2. Pin Assignment Diagram
Table 7-1. KS24L321/641 Pin Descriptions
Name
A0, A1, A2
Type
Input
Description
Input pins for device address selection. To configure a device
address, these pins should be connected to the V
CC
or V
SS
of the
device.
Ground pin.
Bi-directional data pin for the I
2
C-bus serial data interface. Schmitt
trigger input and open-drain output. An external pull-up resistor
must be connected to V
DD.
Schmitt trigger input pin for serial clock input.
Input pin for hardware write protection control. If you tie this pin to
V
CC,
the write function is disabled to protect previously written data
in the entire memory; if you tie it to V
SS
, the write function is
enabled.
Single power supply.
Circuit
Number
1
V
SS
SDA
–
I/O
–
3
SCL
WP
Input
Input
2
1
V
CC
–
–
NOTE:
See the following page for diagrams of pin circuit types 1, 2, and 3.
7-3
KS24L321/641 SERIAL EEPROM
DATA SHEET
A0, A1,
A2, WP
SCL
Noise
Filter
Figure 7-3. Pin Circuit Type 1
Figure 7-4. Pin Circuit Type 2
SDA
Data Out
V
SS
Noise
Filter
Data In
Figure 7-5. Pin Circuit Type 3
7-4
DATA SHEET
KS24L321/641 SERIAL EEPROM
FUNCTION DESCRIPTION
I
2
C-BUS INTERFACE
The KS24L321/641 supports the I
2
C-bus serial interface data transmission protocol. The two-wire bus consists of
a serial data line (SDA) and a serial clock line (SCL). The SDA and the SCL lines must be connected to V
CC
by a
pull-up resistor that is located somewhere on the bus.
Any device that puts data onto the bus is defined as a “transmitter” and any device that gets data from the bus is
a “receiver.” The bus is controlled by a master device which generates the serial clock and start/stop conditions,
controlling bus access. Using the A0, A1, and A2 input pins, up to eight KS24L321/641 devices can be connected
to the same I
2
C-bus as slaves (see Figure 7-6). Both the master and slaves can operate as a transmitter or a
receiver, but the master device determines which bus operating mode would be active.
Vcc
Vcc
R
R
SDA
SCL
Slave 1
Bus Master
(Transmitter/
Receiver)
MCU
To Vcc or Vss
To Vcc or Vss
To Vcc or Vss
To Vcc or Vss
KS24L321/641
Tx/Rx
A0 A1 A2
Slave 2
KS24L321/641
Tx/Rx
A0 A1 A2
Slave 3
KS24L321/641
Tx/Rx
A0 A1 A2
Slave 8
KS24L321/641
Tx/Rx
A0 A1 A2
Figure 7-6. Typical Configuration
7-5
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