PRELIMINARY
Notice. This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI ICs (AV COMMON)
M52795SP/FP
AV SWITCH with I2C BUS CONTROL
DESCRIPTION
The M52795 is AV switch semiconductor integrated circuit with
I2C bus control .
This IC contains 2-channels of 4-input audio switches and 2-
channels of 4-input video switches. Each channel can be
controled independently .
The video switches contain amplifiers can be controled a gain of
output 0dB or 6dB .
PIN CONFIGURATION ( TOP VIEW )
FEATURES
•Video and stereo sound switches in one package
•Wide frequency range ( video switch )...........DC~20MHz
•High separation ( video switch )
..................Crosstalk -60dB ( typ. ) at 1MHz
•Two types of packages are provided : SDIP with a lead pitch of
1.778mm ( M52795SP ) ; and SOP with a lead pitch of 1.27mm
( M52795FP ) .
VCC
Lch 2 IN
VIDEO 2 IN
Rch 2 IN
Lch 3 IN
VIDEO 3 IN
Rch 3 IN
Lch 4 IN
VIDEO 4 IN
Rch 4 IN
SCL
SDA
DC
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
D5
D4
Lch T IN
TUNER IN
Rch T IN
Lch 1 OUT
V 1 OUT
Rch 1 OUT
Lch 2 OUT
V 2 OUT
Rch 2 OUT
BIAS
CHIP SELECT
GND
APPLICATION
Video equipment
Outline 28P4B
(Lead pitch :1.778mm)
PIN CONFIGURATION ( TOP VIEW )
RECOMMENDED OPERATING CONDITION
Supply voltage
Rated supply voltage
Maximum output current
4.7V~9.3V
5V,9V
32mA(at 9V)
VCC
Lch 2 IN
VIDEO 2 IN
Rch 2 IN
Lch 3 IN
VIDEO 3 IN
Rch 3 IN
Lch 4 IN
VIDEO 4 IN
Rch 4 IN
SCL
SDA
DC
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
D5
D4
Lch T IN
TUNER IN
Rch T IN
Lch 1 OUT
V 1 OUT
Rch 1 OUT
Lch 2 OUT
V 2 OUT
Rch 2 OUT
BIAS
CHIP SELECT
GND
Outline 28P2W-A
(Lead pitch :1.27mm)
MITSUBISHI
1-9
AUG.'98
PRELIMINARY
Notice. This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI ICs (AV COMMON)
M52795SP/FP
AV SWITCH with I2C BUS CONTROL
BLOCK DIAGRAM
VCC
TUNER IN
VIDEO 2 IN
VIDEO 3 IN
VIDEO 4 IN
1
25
3
6
9
V-SW1
0/6dB
22
V 1 OUT
0/6dB
19
V-SW2
V 2 OUT
Rch T IN
Rch 2 IN
Rch 3 IN
Rch 4 IN
24
4
7
10
R-MODE2
R-SW1
R-MODE1
R
M
L
0dB
21
Rch 1 OUT
R-SW2
Lch T IN
Lch 2 IN
Lch 3 IN
Lch 4 IN
R
M
L
L-MODE1
0dB
18
Rch 2 OUT
26
2
7
5
8
L-MODE2
L-SW1
L
M
R
0dB
23
Lch 1 OUT
L-SW2
L
M
R
0dB
20
12
11
Lch 2 OUT
SDA
SCL
BIAS
17
BIAS
15
GND
13
I C Control
14
27
28
16
CHIP SELECT
2
DC
DD
D4
D5
MITSUBISHI
2-9
AUG.'98
PRELIMINARY
Notice. This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI ICs (AV COMMON)
M52795SP/FP
AV SWITCH with I2C BUS CONTROL
DESCRIPTION OF PIN
Pin No.
1
2
4
5
7
8
10
24
26
3
6
9
25
Name
VCC
Lch 2 IN
Rch 2 IN
Lch 3 IN
Rch 3 IN
Lch 4 IN
Rch 4 IN
Rch T IN
Lch T IN
VIDEO 2 IN
VIDEO 3 IN
VIDEO 4 IN
TUNER IN
Peripheral circuit pins
DC voltage(V)
9V
4.7V
Remarks
5
~
9V
30K
3.6V
Clamp in
11
SCL
V
IL
max.=1.5V
V
IH
min.=3.0V
12
SDA
V
IL
max.=1.5V
V
IH
min.=3.0V
V
OL
max.=0.4V
(at Iin=3mA)
13
14
27
28
DC
DD
D4
D5
V
OL
max.=0.4V
(at Iin=1mA)
MITSUBISHI
3-9
AUG.'98
PRELIMINARY
Notice. This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI ICs (AV COMMON)
M52795SP/FP
AV SWITCH with I2C BUS CONTROL
DESCRIPTION OF PIN (cont.)
Pin No.
15
16
Name
GND
CHIP
SELECT
Peripheral circuit pins
DC voltage(V)
Remarks
SLAVE
ADDRESS
0~1.5V-------90H
2.5V~Vcc----92H
OPEN--------90H
70K
30K
17
BIAS
4.2V
30K
18
20
21
23
Rch 2 OUT
Lch 2 OUT
Rch 1 OUT
Lch 1 OUT
4.0V
1.5K 1.5K
15K
19
22
V 2 OUT
V 1 OUT
SYNC CHIP
DC=2.9V
5K 5K
MITSUBISHI
4-9
AUG.'98
PRELIMINARY
Notice. This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI ICs (AV COMMON)
M52795SP/FP
AV SWITCH with I2C BUS CONTROL
I C BUS
I
2
C BUS(Inter IC BUS)is multi master bus system developed by PHILIPS . Two wires ( SDA - serial data,
SCL - serial clock ) realize functions of start , stop , transferring data , synchronization and arbitration. The
output stages of device connected to the bus must have an open drain or open collector in order to perform the
wired-AND function .
2
SDA
A
MSB
SCL
S
P
A
MSB
LSB
LSB
1
2
3
4
5
6
7
8
9
1
2
9
S ; Start condition, a high to low transition of the SDA line while SCL is high
P ; Stop condition, a low to high transition of the SDA line while SCL is high
A ; Acknownledge
Every byte put on the SDA line must be 8-bits long . Each byte has to be followed by an acknowledge bit. Data
is transferred with the most significant bit (MSB ) first . The data on the SDA line must be stable during the
HIGH period of the clock . The HIGH or LOW state of the data line can only change when the clock signal on
the SCL line is LOW .
CONTROL
This IC controls 2-channel switchs with 2-byte data ( DATA1 and DATA2 ) . SW1 is controled by
DATA1 ,
SW2 is controled by DATA2 .
S
SLAVE ADDRESS A
DATA1
A
DATA2
A
P
S : Start
A : Acknowledge
P : Stop
SLAVE ADDRESS
1
0
0
1
0
0
X
0
R/W bit
Usually ` 0 ` ( W : Master transmitter transmits to slave
receiver )
Possible to select
16PIN Hi:1,Lo:0
5-9
AUG.'98
MITSUBISHI
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