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5962H9653401VCA

Description
D Flip-Flop, AC Series, 2-Func, Positive Edge Triggered, 1-Bit, Complementary Output, CMOS, CDIP14, SIDE BRAZED, CERAMIC, DIP-14
Categorylogic    logic   
File Size233KB,10 Pages
ManufacturerCobham Semiconductor Solutions
Download Datasheet Parametric View All

5962H9653401VCA Overview

D Flip-Flop, AC Series, 2-Func, Positive Edge Triggered, 1-Bit, Complementary Output, CMOS, CDIP14, SIDE BRAZED, CERAMIC, DIP-14

5962H9653401VCA Parametric

Parameter NameAttribute value
Parts packaging codeDIP
package instructionDIP,
Contacts14
Reach Compliance Codeunknown
ECCN code3A001.A.1.A
seriesAC
JESD-30 codeR-CDIP-T14
JESD-609 codee0
length19.43 mm
Logic integrated circuit typeD FLIP-FLOP
Number of digits1
Number of functions2
Number of terminals14
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Output polarityCOMPLEMENTARY
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeDIP
Package shapeRECTANGULAR
Package formIN-LINE
propagation delay (tpd)21 ns
Certification statusNot Qualified
Filter levelMIL-PRF-38535 Class V
Maximum seat height5.08 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyCMOS
Temperature levelMILITARY
Terminal surfaceTIN LEAD
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
total dose1M Rad(Si) V
Trigger typePOSITIVE EDGE
width7.62 mm
minfmax71 MHz
Base Number Matches1
Standard Products
UT54ACS74/UT54ACTS74
Dual D Flip-Flops with Clear & Preset
Datasheet
November 2010
www.aeroflex.com/logic
FEATURES
1.2μ
CMOS
- Latchup immune
High speed
Low power consumption
Single 5 volt supply
Available QML Q or V processes
Flexible package
- 14-pin DIP
- 14-lead flatpack
UT54ACS74 - SMD 5962-96534
UT54ACTS74 - SMD 5962-96535
DESCRIPTION
The UT54ACS74 and the UT54ACTS74 contain two indepen-
dent D-type positive triggered flip-flops. A low level at the
Preset or Clear inputs sets or resets the outputs regardless of the
levels of the other inputs. When Preset and Clear are inactive
(high), data at the D input meeting the setup time requirement
is transferred to the outputs on the positive-going edge of the
clock pulse. Following the hold time interval, data at the D
input may be changed without affecting the levels at the outputs.
The devices are characterized over full military temperature
range of -55°C to +125°C.
FUNCTION TABLE
INPUTS
PRE
L
H
L
H
H
H
CLR
H
L
L
H
H
H
CLK
X
X
X
L
D
X
X
X
H
L
X
OUTPUT
Q
H
L
H
1
PINOUTS
14-Pin DIP
Top View
CLR1
D1
CLK1
PRE1
Q1
Q1
V
SS
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
DD
CLR2
D2
CLK2
PRE2
Q2
Q2
14-Lead Flatpack
Top View
CLR1
D1
CLK1
PRE1
Q1
Q1
V
SS
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
DD
CLR2
D2
CLK2
PRE2
Q2
Q2
LOGIC SYMBOL
PRE1
CLK1
D1
CLR1
PRE2
CLK2
D2
CLR2
(4)
(3)
(2)
(1)
(10)
(11)
(12)
(13)
(9)
(8)
Q2
Q2
S
C1
D1
R
(5)
(6)
Q1
Q1
Q
L
H
H
L
H
Q
o
1
H
L
Q
o
Note:
1. The output levels in this configuration are not guaranteed to meet the minimum
levels for V
OH
if the lows at preset and clear are near V
IL
maximum. In
addition, this configuration is nonstable; that is, it will not persist when either
preset or clear returns to its inactive (high) level.
Note:
1. Logic symbol in accordance with ANSI/IEEE standard 91-1984 and IEC
Publication 617-12.
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