M5-384/120-10HC datasheet, PDF

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M5-384/120-10HC: DescriptionEE PLD, 7.5 ns, PQFP100; CategoryProgrammable logic devices Programmable logic; File Size536KB，47 Pages; ManufacturerLattice; Websitehttp://www.latticesemi.com

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M5-384/120-10HC Overview

EE PLD, 7.5 ns, PQFP100

M5-384/120-10HC Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Lattice
Parts packaging code	QFP
package instruction	HQFP, HQFP160,1.2SQ,20
Contacts	160
Reach Compliance Code	unknow
ECCN code	EAR99
Other features	YES
maximum clock frequency	58.8 MHz
In-system programmable	YES
JESD-30 code	S-PQFP-G160
JESD-609 code	e0
JTAG BST	YES
length	28 mm
Humidity sensitivity level	3
Dedicated input times
Number of I/O lines	120
Number of macro cells	384
Number of terminals	160
Maximum operating temperature	70 °C
Minimum operating temperature
organize	0 DEDICATED INPUTS, 120 I/O
Output function	MACROCELL
Package body material	PLASTIC/EPOXY
encapsulated code	HQFP
Encapsulate equivalent code	HQFP160,1.2SQ,20
Package shape	SQUARE
Package form	FLATPACK, HEAT SINK/SLUG
power supply	5 V
Programmable logic type	EE PLD
propagation delay	10 ns
Certification status	Not Qualified
Maximum seat height	4.1 mm
Maximum supply voltage	5.25 V
Minimum supply voltage	4.75 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn85Pb15)
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	QUAD
width	28 mm

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MACH 5 CPLD Family

Fifth Generation MACH Architecture

FEATURES

High logic densities and I/Os for increased logic integration

— 128 to 512 macrocell densities

— 68 to 256 I/Os

Wide selection of density and I/O combinations to support most application needs

— 6 macrocell density options

— 7 I/O options

— Up to 4 I/O options per macrocell density

— Up to 5 density & I/O options for each package

Performance features to ﬁt system needs

— 5.5 ns t

Commercial, 7.5 ns t

Industrial

— 182 MHz f

CNT

— Four programmable power/speed settings per block

Flexible architecture facilitates logic design

— Multiple levels of switch matrices allow for performance-based routing

— 100% routability and pin-out retention

— Synchronous and asynchronous clocking, including dual-edge clocking

— Asynchronous product- or sum-term set or reset

— 16 to 64 output enables

— Functions of up to 32 product terms

Advanced capabilities for easy system integration

— 3.3-V & 5-V JEDEC-compliant operations

— IEEE 1149.1 compliant for boundary scan testing

— 3.3-V & 5-V in-system programmable via IEEE 1149.1 Boundary Scan Test Access Por

— PCI compliant (-5/-6/-7/-10/-12 speed grades)

— Safe for mixed supply voltage system design

— Bus-Friendly™ Inputs & I/Os

— Individual output slew rate control

— Hot socketing

— Programmable security bit

Advanced E

CMOS process provides high performance, cost effective solutions

Supported by ispDesignEXPERT™ software for rapid logic development

— Supports HDL design methodologies with results optimized for MACH 5 devices

— Flexibility to adapt to user requirements

— Software partnerships that ensure customer success

Lattice and Third-party hardware programming support

— LatticePRO™ software for in-system programmability support on PCs and Automat

Equipment

— Programming support on all major programmers including Data I/O, BP Microsystem

and System General

Publication#

20446

Amendment/

Rev:

Issue Date:

September 2000

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