AVS
Technology
DESCRIPTION
The AV2636 is a high performance, low power
stereo audio digital to analog converter (DAC). It
is designed for high performance audio
applications such as CD player, DVD player,
home theater systems, digital TVs and set top
boxes. Based on the state of the art multi-bit
∆−Σ
modulator, it also includes the digital
interpolation filters, digital volume control, digital
de-emphasis and analog low pass filters. It has
no linearity drift due to time and temperature. It
also has high tolerance to clock jitter.
The device has a serial audio interface that
accepts 16/18/20/24 digital data in I
2
S, Right-
justified or DSP mode. It can work at auto-detect
mode or programmable mode with a two-wire
serial command interface. Audio sample rates
from 8kHz to 192kHz are supported.
FEATURES
•
•
•
•
•
•
•
•
•
•
AV2636
24-bit 192kHz Stereo Audio DAC
SNR: 102 dB
THD+N: -90 dB
Input Sample rate: 8kHz – 192kHz
Input data resolution: 16/18/20/24 bits
Digital De-Emphasis for 32k/44.1k/48kHz
Digital Volume Control
Mute Control
Single Power Supply 2.2V – 3.6V
Low Clock Jitter Sensitivity
Small 14-pin SOIC Package
APPLICATIONS
•
•
•
•
DVD/CD Player
Home Theatre Systems
Digital TV and Set-Top Boxes
Electronic Music Instrument
CHIP BLOCK DIAGRAM
SC
SF
SD
SERIAL
AUDIO
INTERFACE
INTERPOLATION
DIGITAL
FILTERS
MULTI-LEVEL
∆−Σ
MODULATOR
DAC
LOW PASS
FILTER
LOW PASS
FILTER
AOUTL
DAC
AOUTR
CONTROL INTERFACE
FMTC
FMTD
MUTE
MODE
MCK
VDD
VCM
GND
AVS Technology, Inc.
www.avstech.com
1-16
August 18, 2004
AV2636
PIN CONFIGURATION
Product Datasheet
SF
SD
SC
NC
VCM
AOUTR
GND
1
2
3
4
5
6
7
14
13
12
MCK
FMTD
FMTC
MODE
MUTE
AOUTL
VDD
AV2636
11
10
9
8
PIN DESCRIPTION
Pin Name
SF
SD
SC
(NC)
VCM
AOUTR
GND
VDD
AOUTL
MUTE
MODE
FMTC
Pin
1
2
3
4
5
6
7
8
9
10
11
12
Type
Digital Input
Digital Input
Digital Input
-
Analog Output
Analog Output
Supply
Supply
Analog Output
Digital Input
Digital Input
Digital Input
Description
Sample rate frame clock input.
Audio data input. It can be 16/18/20/24 bit in 2’s complement
format.
Serial audio data bit clock input.
No Connection
Common mode voltage output. Connect to 10uF cap in parallel with
0.1uF cap.
Right channel analog audio signal output.
Ground supply. Need a solid ground plane.
Power supply. Need a clean power supply.
Left channel analog audio signal output.
Mute control with internal pull down.
High = Mute on.
Low = Mute off.
Chip operation mode selection with internal pull down.
High = Programmable mode.
Low = Auto-detect mode.
Dual functional pin. Its function is controlled by the MODE pin.
Internal pull up.
When MODE = High, FMTC = Serial clock in control interface.
When MODE = Low, FMTC = De-Emphasis: On (high) / Off (low).
Dual functional pin. Its function is controlled by the MODE pin.
Internal pull up. Needs an external 4.7kΩ to VDD.
When MODE = High, FMTD = Serial data in control interface.
When MODE = Low, FMTD = Data input format select:
High = 16-24 bit I2S or 16 bit DSP ‘early’
Low = 16 bit right justified or 16 bit DSP ‘late’
External master clock input. The clock frequency depends on the
audio sample rate.
FMTD
13
Digital I/O
MCK
14
Digital Input
AVS Technology, Inc.
www.avstech.com
2-16
August 18, 2004
AV2636
ORDERING INFORMATION
PRODUCT
AV2636
PACKAGE
14 pin SOIC
TEMPERATURE RANGE
-25˚C — +85˚C
Product Datasheet
ELECTROSTATIC DISCHARGE SENSITIVITY
The device of integrated circuits is manufactured on CMOS process. It can be damaged by ESD. AVS
Technology recommends that the device be handled with appropriate ESD precautions. Improper
handling and installation procedures can cause damage to the device.
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings are the limiting values of the stress. Operation beyond these limits may cause
permanent damage to the device. Normal operation is not guaranteed at these limits.
Symbol
VDD
Vi
Ai
T
A
Tstg
Tj
Tsol
Tvsol
Characteristics
Power supply voltage (Measured to GND)
Digital input voltage range
Digital input forced current
Ambient operating temperature range
Storage temperature range
Junction temperature (Plastic package)
Lead soldering temperature (10 sec., ¼” from pin)
Vapor phase soldering (1 minute)
Min
-0.3
GND – 0.3
-100
-25
-65
-65
Max
+3.6
VDD + 0.3
+100
+125
+150
+150
+240
+220
Units
V
V
mA
˚C
˚C
˚C
˚C
˚C
RECOMMENDED OPERATING CONDITIONS
Symbol
VDD
GND
MCK
T
A
Characteristics
Power supply voltage
Ground
Master clock frequency
Ambient operating temperature range
Min
2.2
-25
Typical
3.3
0
Max
3.6
75
85
Units
V
V
MHz
˚C
AVS Technology, Inc.
www.avstech.com
3-16
August 18, 2004
AV2636
Product Datasheet
ELECTRICAL CHARACTERISTICS
(Test conditions: VDD = 3.3V, GND = 0V, T
A
= +25˚C, fs = 48kHz, MCK = 256fs unless otherwise stated.
The measurement bandwidth is from 20Hz to 20kHz.)
PARAMETERS
SYMBOL
MIN
TYP
MAX
UNITS
DC Electrical Characteristics
Supply current (VDD = 3.3V)
I
DD
10
mA
Supply current (VDD = 2.5V)
I
DD
7
mA
Digital I/O Levels (TTL Level)
Digital input high level
V
IH
2.0
V
Digital input low level
V
IL
0.8
V
Digital output high level (I
OH
= 2mA)
V
OH
VDD–0.2
V
Digital output low level (I
OL
= 2mA)
V
OL
GND+0.2
V
Analog Characteristics
Reference voltage
VCM
VDD/2
V
Full scale analog output level
AOUT
VDD/3.3
Vrms
Minimum resistive load
R
L
10
kΩ
Maximum capacitive load
C
L
100
pF
Output DC level
VDD/2
V
DAC Analog Output Performance
(Test load R
L
= 10kΩ, C
L
= 10pF)
VDD = 3.3V SNR
102
dB
THD+N
(1kHz, 0dBFs input)
-90
dB
Dynamic Range
(1kHz, -60dBFs input)
98
dB
VDD = 2.5V SNR
100
dB
THD+N
(1kHz, 0dBFs input)
-90
dB
Dynamic Range
(1kHz, -60dBFs input)
96
dB
Channel separation (1kHz)
-95
dB
Interchannel gain mismatch
0.1
dB
Program gain range
-∞
+6
dB
Notes:
1. SNR is measured as the ratio of output level with 1kHz full scale signal, to output level with all zero
signal into the digital input. The measurement is over 20Hz to 20kHz bandwidth with a ‘A-weight’ filter.
2. THD is measured at the output with 1kHz full scale signal into the digital input. The measurement is
over 20Hz to 20kHz bandwidth.
3. Dynamic Range is the ratio of maximum output over minimum output. It is normally measured by
THD+N at the output with an input signal that is 60dB below full scale. The 60dB is then added back
to the THD+N value for the final result.
4. Channel separation is also known as channel cross talk. It is measured by sending a 1kHz full scale
signal into one channel and measuring the output value at the other channel.
5. All measurements are done with a 20kHz low pass filter. Fail to use the filter will result in reduced
performance reading.
6. The VCM pin should be decoupled with a 10uF capacitor in parallel with a 0.1uF capacitor. Smaller
value may result in reduced performance.
AVS Technology, Inc.
www.avstech.com
4-16
August 18, 2004
AV2636
Product Datasheet
OPERATING MODE
The AV2636 can operate at two modes. They are auto-detect mode and programmable mode. The
‘MODE’ pin status (High/Low) determines which mode the device will be operated. If MODE = Low (pull to
GND or not connected using internal pull down), the device will be operated at auto-detect mode. If
MODE = High (pull to VDD), the device will be operated at programmable mode. The basic functions of
the two modes are described as follows:
•
Auto-detect mode:
The relation between sample rate and master clock frequency is auto detected.
De-emphasis and serial interface mode are determined by FMTC and FMTD pins.
•
Programmable mode:
The device operation will be set by on chip control registers that can be
accessed through a two-wire command interface.
AUDIO DATA SAMPLE RATE AND MASTER CLOCK FREQUENCY
The AV2636 supports various audio data sample rate (fs) from 8kHz to 192kHz. The typical audio sample
rates are 32kHz, 44.1kH, 48kHz, 96kHz and 192kHz. The master clock (MCK) can be of 64fs to 384fs
depending on the operation mode. MCK is an input clock that operates the internal digital filters. Other on
chip clocks are also derived from MCK.
The on-chip master clock detection circuit automatically determines the relationship of master clock
frequency and audio sample rate. The counting error is set to be ±8 master clock cycles. If the error is
larger than the threshold, the DAC output will be shut down and auto muted.
The master clock has to be synchronized with the serial audio data frame signal ‘SF’. SF is also called left
and right data frame signal. The phase difference and clock jitters can be tolerated.
Sample
Rate (fs)
32 kHz
44.1 kHz
48 kHz
88.2 kHz
96 kHz
192 kHz
Note:
* Only available at programmable mode.
64fs
N/A
N/A
N/A
N/A
N/A
12.288
Master Clock Frequency MCK (MHz)
96fs
128fs
192fs
256fs
N/A
N/A
N/A
8.192
N/A
N/A
N/A
11.2896
N/A
N/A
N/A
12.288
N/A
11.1896
16.9344
22.5792
N/A
12.288
18.432
24.576
18.432
24.576
36.864
49.152*
384fs
12.288
16.9344
18.432
33.8688
36.864
73.728*
AVS Technology, Inc.
www.avstech.com
5-16
August 18, 2004
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