a
FEATURES
35 MSPS Encode Rate
16 pF Input Capacitance
550 mW Power Dissipation
Industry-Standard Pinouts
MIL-STD-883 Compliant Versions Available
APPLICATIONS
Professional Video Systems
Special Effects Generators
Electro-Optics
Digital Radio
Electronic Warfare (ECM, ECCM, ESM)
NLINV
12
NMINV
28
V
IN 23
R
T 18
Monolithic 8-Bit
Video A/D Converter
AD9048
FUNCTIONAL BLOCK DIAGRAM
AD9048
1
R
2
R
127
R/2
R
M 27
R/2
128
E
N
C
O
D
I
N
G
L
O
G
I
C
1
D1 (MSB)
2
D2
3
D3
L
A
T
C
H
4
D3
13
D5
14
D6
15
D7
16
D8 (LSB)
R
R
254
GENERAL DESCRIPTION
R
B 26
CONVERT
17
6
10
7
8
255
The AD9048 is an 8-bit, 35 MSPS flash converter, made on
a high speed bipolar process, which is an alternate source for
the TDC1048 unit, and offers enhancements over its
predecessor. Lower power dissipation makes the AD9048
attractive for a variety of system designs.
Because of its wide bandwidth, it is an ideal choice for real-time
conversion of video signals. Input bandwidth is flat with no
missing codes.
Clocked latching comparators, encoding logic, and output
buffer registers operating at minimum rates of 35 MSPS pre-
clude a need for a sample-and-hold (S/H) or track-and-hold
(T/H) in most system designs using the AD9048. All digital
control inputs and outputs are TTL compatible.
Devices operating over two ambient temperature ranges and
with two grades of linearity are available. Linearities of either
0.5 LSB or 0.75 LSB can be ordered for a commercial range of
0°C to 70°C or extended case temperatures of –55°C to +125°C.
9
5
11
19
25
V
CC
V
EE
DGND
AGND
Commercial versions are packaged in 28-lead DIPs; extended
temperature versions are available in ceramic DIP and ceramic
LCC packages. Both commercial units and MIL-STD-883 units
are standard products.
The AD9048 A/D converter is available in versions compliant
with MIL-STD-883. Refer to the Analog Devices
Military Prod-
ucts Databook
or current AD9048/883B data sheet for detailed
specifications.
REV. F
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© 2003 Analog Devices, Inc. All rights reserved.
AD9048–SPECIFICATIONS
(typical with nominal supplies, unless otherwise noted.)
ABSOLUTE MAXIMUM RATINGS
1
V
CC
to DGND . . . . . . . . . . . . . . . . . –0.5 V DC to +7.0 V DC
AGND to DGND . . . . . . . . . . . . . . –0.5 V DC to +0.5 V DC
V
EE
to AGND . . . . . . . . . . . . . . . . . +0.5 V DC to –7.0 V DC
V
IN
, V
RT
, or V
RB
to AGND . . . . . . . . . . . . . . . . . 0.5 V to V
EE
V
RT
to V
RB
. . . . . . . . . . . . . . . . . . . . –2.2 V DC to +2.2 V DC
CONV, NMINV or NLINV to DGND–0.5 V DC to +5.5 V DC
Applied Output Voltage to DGND –0.5 V DC to +5.5 V DC
2
Applied Output Current, Externally Forced
. . . . . . . . . . . . . . . . . . . . . . . . . . . . –1.0 mA to +6.0 mA
3, 4
Output Short-Circuit Duration . . . . . . . . . . . . . . . . . 1.0 sec
5
Operating Temperature Range (Ambient)
AD9048JJ/KJ/JQ/KQ . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
AD9048SE/SQ/TE/TQ . . . . . . . . . . . . . . –55°C to +125°C
Maximum Junction Temperature (Plastic) . . . . . . . . . 150°C
6
Maximum Junction Temperature (Hermetic) . . . . . . . 150°C
6
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . 300°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
ELECTRICAL CHARACTERISTICS
(V
Parameter (Conditions)
RESOLUTION
DC ACCURACY
Differential Nonlinearity
Integral Nonlinearity
No Missing Codes
INITIAL OFFSET ERROR
Top of Reference Ladder
Bottom of Reference Ladder
Offset Drift Coefficient
ANALOG INPUT
Input Voltage Range
Input Bias Current
7
Input Resistance
Input Capacitance
Full Power Bandwidth
8
REFERENCE INPUT
Positive Reference Voltage
9
Negative Reference Voltage
9
Differential Reference Voltage
Reference Ladder Resistance
Ladder Temperature Coefficient
Reference Ladder Current
Reference Input Bandwidth
DYNAMIC PERFORMANCE
10
Conversion Rate
Aperture Delay
Aperture Uncertainty (Jitter)
Output Delay (t
PD
)
Output Hold Time (t
OH
)
11
Transient Response
12
Overvoltage Recovery Time
13
Rise Time
Fall Time
Output Time Skew
14
NMINV and NLINV INPUTS
0.4 V Input Current
2.4 V Input Current
5.5 V Input Current
CONVERT INPUT
Logic “1” Voltage
Logic “0” Voltage
Logic “1” Current
Logic “0” Current
Input Capacitance
Convert Pulsewidth (LOW)
Convert Pulsewidth (HIGH)
25°C
Full
25°C
Full
Full
25°C
Full
25°C
Full
Full
Full
25°C
Full
25°C
Full
25°C
25°C
Full
Full
Full
Full
Full
Full
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
Full
Full
Full
Full
Full
Full
Full
25°C
25°C
25°C
I
VI
I
VI
VI
I
VI
I
VI
V
V
I
VI
I
VI
IV
IV
V
V
V
VI
V
VI
V
I
IV
IV
I
I
IV
V
I
I
I
VI
VI
VI
VI
VI
VI
VI
IV
I
I
Temp
Test
Level
CC
= +5.0 V; V
EE
= –5.2 V; Differential Reference Voltage = 2.0 V, unless otherwise noted.)
AD9048KJ/KQ
Min Typ Max
8
0.4
0.6
0.75
1.0
0.75
1.0
0.3
0.4
Guaranteed
12
12
8
8
5
4
20
–2.1;
+0.1
36
60
100
300
16
15
20
10
12
12
8
8
0.5
0.75
0.5
0.75
AD9048SE/SQ
Min Typ Max
8
0.4
0.6
Guaranteed
5
4
20
–2.1;
+0.1
36
60
100
300
16
15
0.0
–2.0
2.0
60
0.22
23
10
38
2.4
25
9
8
6
8
4.5
20
10
12
12
8
8
0.75
1.0
0.75
1.0
AD9048TE/TQ
Min Typ Max
8
0.3
0.4
Guaranteed
5
4
20
–2.1;
+0.1
36 60
100
300
16
15
20
12
12
8
8
mV
mV
mV
mV
µV/°C
0.5
0.75
0.5
0.75
Unit
Bits
LSB
LSB
LSB
LSB
AD9048JJ/JQ
Min Typ Max
8
Guaranteed
5
4
20
–2.1;
+0.1
36
60
100
300
16
15
0.0
–2.0
2.0
60
0.22
23
10
38
2.4
25
13
8
6
8
4.5
20
200
40
10
200
40
10
200
40
200
40
V
µA
µA
kΩ
kΩ
pF
MHz
V
V
V
Ω
Ω/°C
mA
MHz
MHz
ns
ps
ns
ns
ns
ns
ns
ns
ns
µA
µA
µA
V
V
µA
µA
pF
ns
ns
30
125
40
30
0.0
–2.0
2.0
60
125
0.22
23
40
10
38
2.4
25
9
8
6
8
4.5
30
125
40
30
0.0
–2.0
2.0
60 125
0.22
23 40
10
38
2.4
25
9
8
6
8
4.5
35
35
5
50
15
5
20
9
14
7
200
150
150
35
5
50
15
5
20
9
14
7
200
150
150
35
5
50
15
5
20
9
14
7
200
150
150
5
50
15
20
9
14
7
200
150
150
5
2.0
0.8
150
500
6
2.0
0.8
150
500
6
2.0
0.8
150
500
6
2.0
0.8
150
500
6
4
18
10
4
18
10
4
18
10
4
18
10
–2–
REV. F
AD9048
Parameter (Conditions)
AC LINEARITY
In-Band Harmonics
DC to 2.438 MHz
15
DC to 9.35 MHz
16
Signal-to-Noise Ratio (SNR)
15
1.248 MHz Input Frequency
17
2.438 MHz Input Frequency
17
1.248 MHz Input Frequency
18
2.438 MHz Input Frequency
18
Signal-to-Noise Ratio (SNR)
16
1.248 MHz Input Frequency
17
9.35 MHz Input Frequency
17
Noise Power Ratio (NPR)
19
Differential Phase
20
Differential Gain
20
DIGITAL OUTPUTS
Logic “1” Voltage
Logic “0” Voltage
Short Circuit Current
5
POWER SUPPLY
Positive Supply Current
Negative Supply Current
Nominal Power Dissipation
Reference Ladder Dissipation
Temp
Test
Level
AD9048JJ/JQ
Min Typ Max
AD9048KJ/KQ
Min Typ Max
AD9048SE/SQ
Min Typ Max
AD9048TE/TQ
Min Typ Max
Unit
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
Full
Full
Full
25°C
Full
25°C
Full
25°C
25°C
I
V
I
I
I
I
I
V
IV
IV
IV
VI
VI
VI
I
VI
I
VI
V
V
47
43.5
43
52.5
52
50
48
44
44
53
53
49
45
44
54
53
45
36.5
1
2
55
48
46
46
55
55
46
40.5
39
1
2
47
43.5
43
52.5
52
43.5
36.5
50
48
44
44
53
53
44
40.5
39
1
2
49
45
44
54
53
45
55
48
46
46
55
55
dBc
dBc
dB
dB
dB
dB
dB
dB
dB
Degree
%
V
V
mA
mA
mA
mA
mA
mW
mW
43.5 44
40.5
36.5 39
46
40.5
36.5 39
1
2
2.4
2.4
0.5
30
34
90
550
45
56
58
110
120
2.4
0.5
30
34
90
550
45
10
11
2.4
0.5
30
34
90
550
45
56
58
110
120
0.5
30
34
90
550
45
56
58
110
120
56
58
110
120
NOTES
1
Maximum ratings are limiting values to be applied individually, and beyond which
the serviceability of the device may be impaired. Functional operation under any of
these conditions is not necessarily implied. Exposure to absolute maximum rating
conditions for extended periods of time may affect device reliability.
2
Applied voltage must be current-limited to specified range.
3
Forcing voltage must be limited to specified range.
4
Current is specified as negative when flowing into the device.
5
Output High; one pin to ground; 1s duration.
6
Typical thermal impedances (no air flow) are as follows:
Ceramic DIP:
θ
JA
= 49°C/W,
θ
JC
= 15°C/W; LCC:
θ
JA
= 69°C/W,
θ
JC
= 21°C/W;
JLCC:
θ
JA
= 59°C/W;
θ
JC
= 19°C/W.
To calculate junction temperature (T
J
), use power dissipation (PD) and thermal
impedance: T
J
= PD (θ
JA
) + T
AMBIENT
= PD (θ
JC
) = + T
CASE
.
7
Measured with V
IN
= 0 V and CONVERT low (sampling mode).
8
Determined by beat frequency testing for no missing codes.
9
V
RT
≥
V
RB
under all circumstances.
Outputs terminated with 40 pF and eight 10
Ω
pull-up resistors.
Interval from 50% point of leading edge CONVERT pulse to change in
output data.
12
For full-scale step input, 8-bit accuracy attained in specified time.
13
Recovers to 8-bit accuracy in specified time after –3 V input overvoltage.
14
Output time skew includes high-to-low and low-to-high transitions as well as
bit-to-bit time skew differences.
15
Measured at 20 MHz encode rate with analog input 1 dB below full scale.
16
Measured at 35 MHz encode rate with analog input 1 dB below full scale.
17
RMS signal to rms noise.
18
Peak signal to rms noise.
19
DC to 8 MHz noise bandwidth with 1.248 MHz slot; four sigma loading;
20 MHz encode.
20
Clock frequency = 4
×
NTSC = 14.32 MHz. Measured with 40-IRE
modulated ramp.
Specifications subject to change without notice.
EXPLANATION OF TEST LEVELS
Test Level I – 100% production tested.
Test Level II – 100% production tested at 25°C and
sample tested at specific temperatures.
Test Level III – Sample tested only.
Test Level IV – Parameter is guaranteed by design and
characterization testing.
Test Level V – Parameter is a typical value only.
Test Level VI – All devices are 100% production tested at
25°C. 100% production tested at temperature
extremes for military temperature devices;
sample tested at temperature extremes for
commercial/industrial devices.
REV. F
–3–
AD9048
ORDERING GUIDE
PIN CONFIGURATIONS
Model
AD9048JJ
AD9048KJ
AD9048JQ
AD9048KQ
AD9048SE/833B
2
AD9048TE/833B
2
AD9048SQ/833B
2
AD9048TQ/833B
2
Linearity
0.75 LSB
0.5 LSB
0.75 LSB
0.5 LSB
0.75 LSB
0.5 LSB
0.75 LSB
0.5 LSB
Temperature
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
–55°C to +125°C
–55°C to +125°C
–55°C to +125°C
–55°C to +125°C
Package
Option
1
J-28A
J-28A
D-28
D-28
E-28A
E-28A
D-28
D-28
DIP (D Package)
(MSB) D1
1
D2
2
D3
D4
3
4
28
NMINV
27
R
M
26
R
B
25
AGND
DGND
5
V
CC
6
V
EE
7
V
EE
8
V
EE
9
AD9048
TOP VIEW
(Not to Scale)
24
NC
23
V
IN
22
NC
21
NC
20
NC
19
AGND
18
R
T
17
CONVERT
16
D8 (LSB)
15
D7
NOTES
1
E = Leadless Ceramic Chip Carrier; J = J-Leaded Ceramic; D = Cerdip.
2
MIL-STD-883 and Standard Military Drawing available.
V
CC
10
DGND
11
NLINV
12
D5
13
D6
14
MECHANICAL INFORMATION
NC = NO CONNECT
Die Dimensions . . . . . 140 mils
×
137 mils
×
21 mils (± 2) mils
Pad Dimensions . . . . . . . . . . . . . . . . . . . . . . . . 4 mils
×
4 mils
Metallization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gold
Backing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . None
Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
EE
Passivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nitride
Die Attach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gold Eutectic
Bond Wire . . . . . . . . . . . . . . . 1 mils Gold; Gold Ball Bonding
LCC (E Package)
D1 (MSB)
NMINV
R
M
D4
D3
D2
R
B
4
3
2
1
28 27 26
DGND
5
V
CC
6
V
EE
7
V
EE
8
V
EE
9
V
CC
10
DGND
11
25
24
AGND
NC
V
IN
NC
NC
NC
AGND
AD9048
TOP VIEW
(Not to Scale)
23
22
21
20
19
AGND
AIN
AGND
12 13 14 15 16 17 18
D7
(LSB) D8
NC
RLOW
RMID
NMINV
MSB
D2
D3
D4
RTOP
CONV
D8
D7
D6
D5
NLINV
R
B 26
R
M 27
NMINV
28
(MSB) D1
1
D2
2
D3
3
D4
4
NC = NO CONNECT
J-Leaded Ceramic (J Package)
AGND
AGND
19
18
17
V
IN
NC
25 24 23 22 21 20
NC
NC
CONVERT
NLINV
D5
D6
R
T
R
T
CONVERT
D8 (LSB)
D7
D6
D5
NLINV
16
15
14
13
12
DGND
DGND
AD9048
(Not to Scale)
(Not to Scale)
TOP VIEW
TOP VIEW
V
CC
V
CC
V
EE
V
EE
V
EE
V
CC
V
CC
DGND
Figure 1. Bonding Diagram
5
6
7
8
9
10 11
DGND
NC = NO CONNECT
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9048 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4–
DGND
V
EE
V
EE
V
CC
V
EE
V
CC
REV. F
AD9048
PIN FUNCTION DESCRIPTIONS
Mnemonic
D1–D8
Description
Eight Digital Outputs. D1 (MSB) is the most
significant bit of the digital output word;
D8 (LSB) is the least significant bit.
One of Two Analog Ground Returns. Both
grounds should be connected together and to
low impedance ground plane near the AD9048.
One of Two Digital Ground Returns. Both
grounds should be connected together and to
low impedance ground plane near the AD9048.
Positive Supply Terminals; Nominally 5.0 V
Negative Supply Terminals; Nominally –5.2 V
Input for Conversion Signal. Sample of analog
input signal taken on rising edge of this pulse.
Mnemonic
R
B
R
M
R
T
V
IN
NMINV
Description
Most Negative Reference Voltage for Internal
Reference Ladder
Midpoint Tap on Internal Reference Ladder
Most Positive Reference Voltage for Internal
Reference Ladder
Analog Input Signal Pin
“Not Most Significant Bit Invert.” In normal
operation, this pin floats high; logic LOW at
NMINV inverts most significant bit of digital
output word [D1 (MSB)].
“Not Least Significant Bit Invert.” In normal
operation, this pin floats high; logic LOW at
NLINV inverts the seven least significant bits
of the digital output word.
AGND
DGND
V
CC
V
EE
CONVERT
NLINV
–5.2V
0.1 F
+5.0V
0.1 F
V
EE
100
AD1
V
IN
510
AD2
CONVERT
V
CC
(MSB) D1
D2
D3
D4
AD9048
–2.0V
R
B
D5
D6
D7
R
T
DIGITAL
GROUND
ALL RESISTORS 5%
ALL CAPACITORS 20%
ALL SUPPLY VOLTAGES 5%
(LSB) D8
ANALOG
GROUND
1k
LOAD
RESISTORS
OPTION #1 (STATIC): AD1 = –2.0V; AD2 = +2.4V
OPTION #2 (DYNAMIC): SEE WAVEFORMS
0V
AD1
640 s
–2.0V
AD2
5 s
V
IH
V
IL
Figure 2. Burn-In Diagram
REV. F
–5–
Electronics Design Contest
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