M48Z35AY
M48Z35AV
256 Kbit (32Kb x8) ZEROPOWER
®
SRAM
s
INTEGRATED ULTRA LOW POWER SRAM,
POWER-FAIL CONTROL CIRCUIT and
BATTERY
READ CYCLE TIME EQUALS WRITE CYCLE
TIME
BATTERY LOW FLAG (BOK)
AUTOMATIC POWER-FAIL CHIP DESELECT
and WRITE PROTECTION
WRITE PROTECT VOLTAGES
(V
PFD
= Power-fail Deselect Voltage):
– M48Z35AY: 4.20V
≤
V
PFD
≤
4.50V
– M48Z35AV: 2.7V
≤
V
PFD
≤
3.0V
28
SNAPHAT (SH)
Battery
s
s
s
28
1
s
1
PCDIP28 (PC)
Battery CAPHAT
SOH28 (MH)
s
SELF-CONTAINED BATTERY in the CAPHAT
DIP PACKAGE
PACKAGING INCLUDES a 28-LEAD SOIC and
SNAPHAT
®
TOP
(to be Ordered Separately)
SOIC PACKAGE PROVIDES DIRECT
CONNECTION for a SNAPHAT TOP which
CONTAINS the BATTERY and CRYSTAL
PIN and FUNCTION COMPATIBLE with
JEDEC STANDARD 32K x8 SRAMs
15
A0-A14
VCC
s
Figure 1. Logic Diagram
s
s
DESCRIPTION
The M48Z35AY/35AV ZEROPOWER
®
RAM is a
32 Kbit x8 non-volatile static RAM that integrates
power-fail deselect circuitry and battery control
logic on a single die. The monolithic chip is avail-
able in two special packages to provide a highly in-
tegrated battery backed-up memory solution.
Table 1. Signal Names
A0-A14
DQ0-DQ7
E
G
W
V
CC
V
SS
April 2000
Address Inputs
Data Inputs / Outputs
Chip Enable
Output Enable
Write Enable
Supply Voltage
Ground
8
DQ0-DQ7
W
E
G
M48Z35AY
M48Z35AV
VSS
AI02781B
1/16
M48Z35AY, M48Z35AV
Figure 2A. DIP Pin Connections
Figure 2B. SOIC Pin Connections
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
28
1
27
2
26
3
25
4
24
5
23
6
7 M48Z35AY 22
8 M48Z35AV 21
20
9
19
10
18
11
17
12
13
16
14
15
AI02782B
VCC
W
A13
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
28
27
2
26
3
25
4
24
5
23
6
7 M48Z35AY 22
8 M48Z35AV 21
20
9
19
10
18
11
17
12
16
13
15
14
AI02783
VCC
W
A13
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
Table 2. Absolute Maximum Ratings
(1)
Symbol
T
A
T
STG
T
SLD (2)
V
IO
V
CC
I
O
P
D
Parameter
Ambient Operating Temperature
Storage Temperature (V
CC
Off)
Grade 1
Grade 6
SNAPHAT
SOIC
Value
0 to 70
–40 to 85
–40 to 85
–55 to 125
260
–0.3 to 7
–0.3 to 7
20
1
Unit
°C
°C
°C
V
V
mA
W
Lead Solder Temperature for 10 seconds
Input or Output Voltages
Supply Voltage
Output Current
Power Dissipation
Note: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational section
of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect
reliability.
2. Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds).
CAUTION:
Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode.
CAUTION:
Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
2/16
M48Z35AY, M48Z35AV
Table 3. Operating Modes
(1)
Mode
Deselect
Write
Read
Read
Deselect
Deselect
V
SO
to V
PFD
(min)
(2)
≤
V
SO
4.5V to 5.5V
or
3.0V to 3.6V
V
CC
E
V
IH
V
IL
V
IL
V
IL
X
X
G
X
X
V
IL
V
IH
X
X
W
X
V
IL
V
IH
V
IH
X
X
DQ0-DQ7
High Z
D
IN
D
OUT
High Z
High Z
High Z
Power
Standby
Active
Active
Active
CMOS Standby
Battery Back-up Mode
Note: 1. X = V
IH
or V
IL
; V
SO
= Battery Back-up Switchover Voltage.
2. See Table 7 for details.
Figure 3. Block Diagram
A0-A14
LITHIUM
CELL
VOLTAGE SENSE
AND
SWITCHING
CIRCUITRY
POWER
32K x 8
SRAM ARRAY
DQ0-DQ7
VPFD
E
W
G
VCC
VSS
AI01619B
The M48Z35AY/35AV is a non-volatile pin and
function equivalent to any JEDEC standard 32K x8
SRAM. It also easily fits into many ROM, EPROM,
and EEPROM sockets, providing the non-volatility
of PROMs without any requirement for special
write timing or limitations on the number of writes
that can be performed. The 28 pin 600mil DIP
CAPHAT™ houses the M48Z35AY/35AV silicon
with a long life lithium button cell in a single pack-
age.
The 28 pin 330mil SOIC provides sockets with
gold plated contacts at both ends for direct con-
nection to a separate SNAPHAT housing contain-
ing the battery. The unique design allows the
SNAPHAT battery package to be mounted on top
of the SOIC package after the completion of the
surface mount process. Insertion of the SNAPHAT
housing after reflow prevents potential battery
damage due to the high temperatures required for
device surface-mounting. The SNAPHAT housing
is keyed to prevent reverse insertion.
3/16
M48Z35AY, M48Z35AV
Table 4. AC Measurement Conditions
Input Rise and Fall Times
Input Pulse Voltages
Input and Output Timing Ref. Voltages
≤
5ns
0 to 3V
1.5V
DEVICE
UNDER
TEST
645Ω
Figure 4. AC Testing Load Circuit
Note that Output Hi-Z is defined as the point where data is no longer
driven.
The SOIC and battery packages are shipped sep-
arately in plastic anti-static tubes or in Tape & Reel
form.
For the 28 lead SOIC, the battery package (i.e.
SNAPHAT) part number is "M4Z28-BR00SH1".
The M48Z35AY/35AV also has its own Power-fail
Detect circuit. The control circuitry constantly mon-
itors the single 5V supply for an out of tolerance
condition. When V
CC
is out of tolerance, the circuit
write protects the SRAM, providing a high degree
of data security in the midst of unpredictable sys-
tem operation brought on by low V
CC
. As V
CC
falls
below approximately 3V, the control circuitry con-
nects the battery which maintains data until valid
power returns.
READ MODE
The M48Z35AY/35AV is in the Read Mode when-
ever W (Write Enable) is high, E (Chip Enable) is
low. The device architecture allows ripple-through
access of data from eight of 264,144 locations in
the static storage array. Thus, the unique address
specified by the 15 Address Inputs defines which
one of the 32,768 bytes of data is to be accessed.
Valid data will be available at the Data I/O pins
within Address Access time (t
AVQV
) after the last
address input signal is stable, providing that the E
and G access times are also satisfied. If the E and
G access times are not met, valid data will be
available after the latter of the Chip Enable Access
time (t
ELQV
) or Output Enable Access time
(t
GLQV
).
The state of the eight three-state Data I/O signals
is controlled by E and G. If the outputs are activat-
CL = 100pF or
5pF
1.75V
CL includes JIG capacitance
AI03211
ed before t
AVQV
, the data lines will be driven to an
indeterminate state until t
AVQV
. If the Address In-
puts are changed while E and G remain active,
output data will remain valid for Output Data Hold
time (t
AXQX
) but will go indeterminate until the next
Address Access.
WRITE MODE
The M48Z35AY/35AV is in the Write Mode when-
ever W and E are low. The start of a write is refer-
enced from the latter occurring falling edge of W or
E. A write is terminated by the earlier rising edge
of W or E. The addresses must be held valid
throughout the cycle. E or W must return high for
a minimum of t
EHAX
from Chip Enable or t
WHAX
from Write Enable prior to the initiation of another
read or write cycle. Data-in must be valid t
DVWH
prior to the end of write and remain valid for t
WHDX
afterward. G should be kept high during write cy-
cles to avoid bus contention; although, if the output
bus has been activated by a low on E and G, a low
on W will disable the outputs t
WLQZ
after W falls.
4/16
M48Z35AY, M48Z35AV
Table 5. Capacitance
(1, 2)
(T
A
= 25 °C)
Symbol
C
IN
C
IO (3)
Parameter
Input Capacitance
Input / Output Capacitance
Test Condition
V
IN
= 0V
V
OUT
= 0V
Min
Max
10
10
Unit
pF
pF
Note: 1. Effective capacitance measured with power supply at 5V.
2. Sampled only, not 100% tested.
3. Outputs deselected.
Table 6. DC Characteristics
(T
A
= 0 to 70 °C or –40 to 85 °C; V
CC
= 4.5V to 5.5V or 3.0v to 3.6V)
Symbol
I
LI (1)
I
LO (1)
I
CC
I
CC1
I
CC2
V
IL (2)
V
IH
V
OL
V
OH
Parameter
Input Leakage Current
Output Leakage Current
Supply Current
Supply Current (Standby) TTL
Supply Current (Standby) CMOS
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
I
OL
= 2.1mA
I
OH
= –1mA
2.4
Test Condition
0V
≤
V
IN
≤
V
CC
0V
≤
V
OUT
≤
V
CC
Outputs open
E = V
IH
E = V
CC
– 0.2V
–0.3
2.2
Min
Max
±1
±5
50
3
3
0.8
V
CC
+ 0.3
0.4
Unit
µA
µA
mA
mA
mA
V
V
V
V
Note: 1. Outputs deselected.
2. Negative spikes of –1V allowed for up to 10ns once per cycle.
Table 7. Power Down/Up Trip Points DC Characteristics
(1)
(T
A
= 0 to 70 °C or –40 to 85 °C)
Symbol
V
PFD
V
PFD
V
SO
V
SO
t
DR (2)
Parameter
Power-fail Deselect Voltage (M48Z35AY)
Power-fail Deselect Voltage (M48Z35AV)
Battery Back-up Switchover Voltage (M48Z35AY)
Battery Back-up Switchover Voltage (M48Z35AV)
Expected Data Retention Time
10
Min
4.2
2.7
Typ
4.35
2.9
3.0
V
PFD
– 100mV
Max
4.5
3.0
Unit
V
V
V
V
YEARS
Note: 1. All voltages referenced to V
SS
.
2. At 25 °C.
5/16
Embedded System
京公网安备 11010802033920号
EEWORLD
