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■
S
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e
Semiconductor IC
2CH Step up and Inverter DC/DC converter
■ P r o d u c t
■ M o d e l
■
■
Physical
F
u
n
c
N a m e
N a m e
BD9642GU
VCSP85H2 (Plastic Mold)
(1)
(2)
(3)
(4)
(5)
(6)
Dimension
t
i
o
n
2CH DC/DC converter （CH1：Step up/CH2：Inverter ）
The output voltage can be set by external resistance. （CH1,CH2 ）
Power MOS FET built-in （CH1only ）
CH1 and CH2 have terminals for enable each other.
Soft start capability （CH1,CH2 ）
Protection function built-in
（Short-circuit protection function、thermal shutdown ）
(7) UVLO operation at low power-supply voltage
(8) Back-gate Control function （CH1only ）
(9) Inverter’s output discharge with output is off. (CH2)
(10) Ultra small WL-CSP package（2.34[mm]×2.34[mm] ）
■ Absolute Maximum Rating （Ta=25[℃]）
Parameter
Symbol
Rating
Unit
Supply voltage
VBAT
-0.3½7
V
Power Dissipation
Pd
390
（※1）
mW
Operating temperature range
Topt
-20½+70
℃
Storage temperature range
Tstg
-55½+150
℃
SW1 terminal current
Isw1
0.5
A
Terminal permissible voltage（※2）
VPIN1
-0.3½7
V
VOUT1/SW1 Terminal input
V
V PIN2
-0.3½15
Permissible voltage
VOUT2 Terminal input
V PIN3
-9½0.7
V
Permissible voltage
Junction temperature
Tjmax
+150
℃
（※1） Derating in done 3.12[mW/℃] for operating above Ta=25 [℃]. (Mount on 1-layer 70.0[mm]×70.0[mm]× 1.6[mm] board.)
(※2) Except for VOUT1,SW1,VOUT2
■ Operating condition （Ta=-20½+70[℃]）
Parameter
Supply voltage
VOUT1 Output voltage setting
range
VOUT2 Output voltage setting
range
Symbol
VBAT
VOUT1RNG
VOUT2RNG
MIN.
2.5
11
-8
Rating
TYP.
3.7
-
-
MAX.
5.5
13
-5.5
Unit
V
V
V
・This product is no antiradiation design.
Status of this document
The Japanese version of this document is the formal specification. A customer may use this translation version only for a reference to
help reading the formal version. If there are any differences in translation version of this document, formal version takes priority.
REV. B
2/4
■Electric
Characteristics
（Unless otherwise specified. VBAT=3.7[V],Ta=25[℃]）
Parameter
[Device]
Current consumption
Shutdown current
VREF output voltage
RT output voltage
[Voltage drop detection Block]
UVLO detection voltage
UVLO return voltage
[CH1（Step up）]
FB1 terminal voltage
Soft start time 1
Oscillation frequency1
Maximum duty cycle 1
PMOS ON resistance
NMOS ON resistance
[CH2（Inverter）]
FB2 terminal voltage
Output voltage accuracy
Soft start time 2
Oscillation frequency 2
Maximum duty cycle 2
PMOS for discharge ON resistance
[XSHDN]
XSHDN H input voltage
XSHDN Ｌ input voltage
XSHDN1,XSHDN2 input current
[GND short detection Block]
Timer latch
GND short detection voltage 1
GND short detection voltage 2
ICCST
ICCOFF
VVREF
VRT
VUVLO1
VUVLO2
VFB1
TSOFT1
FOSC1
DMAX1
RONP1
RONN1
VFB2
VACUCH2
TSOFT2
FOSC2
DMAX2
RONDIS
VIH
VIＬ
IIH1, IIH2
TLATCH
VSHORT1
VSHORT2
-
-
1.930
0.9
2.05
2.10
0.985
1.9
375
88
-
-
0.925
-2.5
1.9
375
88
-
1.5
－
4.63
0.5
0.4
1.19
1.50
0
2.000
1.00
2.15
2.20
1.000
3.8
500
92
1.40
0.45
1.000
0
3.8
500
92
100
－
－
9.25
1
0.5
1.29
2.25
10
2.070
1.1
2.25
2.30
1.015
7.6
625
-
2.24
0.72
1.075
2.5
7.6
625
-
200
－
0.3
18.5
2
0.6
1.39
mA
μA
V
V
V
V
V
ms
KHz
％
Ω
Ω
V
％
ms
KHz
％
Ω
V
V
μA
ms
V
V
XSHDN1=XSHDN2=VBAT
CH1,CH2 output No load
XSHDN1=XSHDN2=GND
RT=100[kΩ]
Symbol
Limit
Min.
Typ.
Max.
Unit
Condition
85％ (RT=100[kΩ])
VOUT1=12[V]
VOUT1=12[V]
*1
85％ (RT=100[kΩ])
VBAT=2.5[V]
XSHDN1, XSHDN2
VBAT = 2.5V ½ 5.5V
Input voltage=3.7[V]
CH1
CH2
*1：Output voltage accuracy VACUCH2=(9.5×VFB2-8.5×VVREF)/-7.5×100
■
Dimension
1PIN MARK
■
Terminal layout of the back chip
VCSP85H2
BD9642
2.34±0.1
2.34±0.1
D
XSHDN1
PGND
SW1
VOUT1
LOT.No
0.25±0.10
C
XSHDN2
VOUT2
AGND
AGND
1.0MAX
S
B
RT
AGND
FB1
0.08 S
15-F 0.30±0.05
0.05 A B
A
D
C
B
A
(F 0.15)INDEX post
0.42±0.1
1
2
3
4
(Unit:mm)
P=0.5×3
B
0.42±0.1
A
VBAT
GATE2
FB2
VREF
1
2
3
4
P=0.5×3
REV. B
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■
Terminal Explanation
Terminal
No.
A1
D4
D3
B3
C3
C4
A4
C2
D2
B4
B1
A2
A3
C1
D1
Terminal
Name
VBAT
VOUT1
SW1
AGND
AGND
AGND
VREF
VOUT2
PGND
FB1
RT
GATE2
FB2
XSHDN2
XSHDN1
Power supply terminal
Function
Step up converter(CH1) output voltage terminal
Step up converter(CH1) Switching terminal
Analog GND terminal
Analog GND terminal
Analog GND terminal
Reference voltage output terminal (2.0V)
Inverter(CH2) output voltage terminal and discharge terminal
Power GND terminal
Step up converter (CH1) Feedback terminal
Register connect terminal for soft-start time.（R
T
=100[kΩ]）
Control terminal （CH2） connect PMOSFET for inverter output.
Step up converter (CH2) Feedback terminal
Shutdown terminal (Shutdown with XSHDN=GND)
(CH2)
Shutdown terminal (Shutdown with XSHDN=GND)
(CH1)
■
Block Diagram
REV. B
4/4
■Notes
On Use
1．Notes for absolute maximum rating
・ Exceeding supply voltage and operating Temp over Absolute Maximum Ratings may cause degradation of IC
and even may destroy the IC. if special mode such that exceeding Absolute Maximum Ratings is expected,
please have safe countermeasure such as adding POLY SWITCH and fuse to avoid from over stressing.
2．Notes for heat design
・Do not exceed the power dissipation (PD) of the package specification rating under actual operation.
3．Short circuit mode between terminals and wrong mounting
・While mounting IC on the board, check direction and position of the IC. If inadequately mounted, the IC may destroy.
Moreover this IC might be destroyed when dust short the terminals between pins or pin and ground. Avoid the
VOUT-GND short-circuit.
4．Radiation
・ Strong electromagnetic radiation can cause operation failures.
5．Notes for Thermal shutdown (TSD)
・Main purpose of TSD is to shutting IC down from runaway effect. It is not to compensate or to protect set
device. Therefore, please do not continuously operate the IC after TSD circuit is activated and/or premise
operations such that TSD circuit function being used.
6．Notes for test of mounted print board
・While connecting capacitor to Low impedance pins, please discharge capacitor by one process by another to
prevent stressing the IC. While mounting and removing the IC to/from the Board in the inspection process, be sure
to turn off the power supply at each actions. Moreover equip ground earth in assembling process for ESD
protection and handle with care during the test and/or transportation.
7．Notes for each input terminal
・This IC is a monolithic IC, and has P
+
isolation and P substrate for the element separation. Therefore, a parasitic PN
junction is firmed in this P-layer and N-layer of each element. For instance, the resistor or the transistor is
connected to the terminal as shown in the figure below. When the GND voltage potential is greater than the voltage
potential at Terminals A or B, the PN junction operates as a parasitic diode. In addition, the parasitic NPN
transistor is formed in said parasitic diode and the N layer of surrounding elements close to said parasitic diode.
These parasitic elements are formed in the IC because of the voltage relation. The parasitic element operating
causes the wrong operation and destruction. Therefore, please be careful so as not to operate the parasitic
elements by applying lower voltage than GND (P substrate) to input terminals. Moreover, please apply each input
terminal with lower than the power-supply voltage or equal to the specified range in the guaranteed voltage when
the power-supply voltage being applied.
Example of simple structure of IC
REV. B
Notice
Notes
No copying or reproduction of this document, in part or in whole, is permitted without the
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The content specified herein is for the purpose of introducing ROHM's products (hereinafter
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which can be obtained from ROHM upon request.
Examples of application circuits, circuit constants and any other information contained herein
illustrate the standard usage and operations of the Products. The peripheral conditions must
be taken into account when designing circuits for mass production.
Great care was taken in ensuring the accuracy of the information specified in this document.
However, should you incur any damage arising from any inaccuracy or misprint of such
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The technical information specified herein is intended only to show the typical functions of and
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