MT41K512M8RH-125AAT:E datasheet, PDF

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MT41K512M8RH-125AAT:E: DescriptionDDR DRAM, 512MX8, CMOS, PBGA78, 9 X 10.50 MM, LEAD FREE, FBGA-78; Categorystorage storage; File Size16MB，211 Pages; ManufacturerMicron Technology; Websitehttp://www.mdtic.com.tw/

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MT41K512M8RH-125AAT:E Overview

DDR DRAM, 512MX8, CMOS, PBGA78, 9 X 10.50 MM, LEAD FREE, FBGA-78

MT41K512M8RH-125AAT:E Parametric

Parameter Name	Attribute value
Maker	Micron Technology
package instruction	TFBGA,
Reach Compliance Code	compliant
access mode	MULTI BANK PAGE BURST
Other features	AUTO/SELF REFRESH
JESD-30 code	R-PBGA-B78
length	10.5 mm
memory density	4294967296 bit
Memory IC Type	DDR DRAM
memory width	8
Number of functions	1
Number of ports	1
Number of terminals	78
word count	536870912 words
character code	512000000
Operating mode	SYNCHRONOUS
organize	512MX8
Package body material	PLASTIC/EPOXY
encapsulated code	TFBGA
Package shape	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE, FINE PITCH
Filter level	AEC-Q100
Maximum seat height	1.2 mm
self refresh	YES
Maximum supply voltage (Vsup)	1.45 V
Minimum supply voltage (Vsup)	1.283 V
Nominal supply voltage (Vsup)	1.35 V
surface mount	YES
technology	CMOS
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
width	9 mm
Base Number Matches	1

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4Gb: x8, x16 Automotive DDR3L SDRAM

Description

Automotive DDR3L SDRAM

MT41K512M8 – 64 Meg x 8 x 8 banks

MT41K256M16 – 32 Meg x 16 x 8 banks

Description

DDR3L SDRAM (1.35V) is a low voltage version of the

DDR3 (1.5V) SDRAM. Refer to the DDR3 (1.5V)

SDRAM data sheet specifications when running in

1.5V compatible mode.

•

Self refresh temperature (SRT)

Automatic self refresh (ASR)

Write leveling

Multipurpose register

Output driver calibration

AEC-Q100

PPAP submission

8D response time

Features

• V

= V

DDQ

= 1.35V (1.283–1.45V)

• Backward compatible to V

= V

DDQ

= 1.5V ±0.075V

– Supports DDR3L devices to be backward com-

patible in 1.5V applications

• Differential bidirectional data strobe

• 8n-bit prefetch architecture

• Differential clock inputs (CK, CK#)

• 8 internal banks

• Nominal and dynamic on-die termination (ODT)

for data, strobe, and mask signals

• Programmable CAS (READ) latency (CL)

• Programmable posted CAS additive latency (AL)

• Programmable CAS (WRITE) latency (CWL)

• Fixed burst length (BL) of 8 and burst chop (BC) of 4

(via the mode register set [MRS])

• Selectable BC4 or BL8 on-the-fly (OTF)

• Self refresh mode

• T

of –40°C to +105°C

– 64ms, 8192-cycle refresh at –40°C to +85°C

– 32ms at +85°C to +105°C

Options

• Configuration

– 512 Meg x 8

– 256 Meg x 16

• FBGA package (Pb-free) – x8

– 78-ball (10.5mm x 12mm) Rev. D

– 78-ball (9mm x 10.5mm) Rev. E

• FBGA package (Pb-free) – x16

– 96-ball (10mm x 14mm) Rev. D

– 96-ball (9mm x 14mm) Rev. E

• Timing – cycle time

– 1.071ns @ CL = 13 (DDR3-1866)

– 1.25ns @ CL = 11 (DDR3-1600)

– 1.5ns @ CL = 9 (DDR3-1333)

– 1.875ns @ CL = 7 (DDR3-1066)

• Product certification

– Automotive

• Operating temperature

– Industrial (–40°C

≤

+95°C)

– Automotive (–40°C

≤

+105°C)

• Revision

Marking

512M8

256M16

-107

-125

-15E

-187E

:D/:E

Table 1: Key Timing Parameters

Speed Grade

-107

1, 2, 3

-125

1, 2

-15E

-187E

Notes:

Data Rate (MT/s)

1866

1600

1333

1066

Target

RCD-

RP-CL

13-13-13

11-11-11

9-9-9

7-7-7

RCD

(ns)

CL (ns)

13.91

13.75

13.5

13.1

13.91

13.75

13.5

13.1

13.91

13.75

13.5

13.1

1. Backward compatible to 1066, CL = 7 (-187E).

2. Backward compatible to 1333, CL = 9 (-15E).

3. Backward compatible to 1600, CL = 11 (-125).

PDF: 09005aef8537e66f

4Gb_auto_DDR3L.pdf - Rev. C 2/14 EN

Products and specifications discussed herein are subject to change by Micron without notice.

Micron Technology, Inc. reserves the right to change products or specifications without notice.

4Gb: x8, x16 Automotive DDR3L SDRAM

Description

Contents

State Diagram ................................................................................................................................................ 11

Functional Description ................................................................................................................................... 12

Industrial Temperature ............................................................................................................................... 12

Automotive Temperature ............................................................................................................................ 12

General Notes ............................................................................................................................................ 13

Functional Block Diagrams ............................................................................................................................. 14

Ball Assignments and Descriptions ................................................................................................................. 16

Package Dimensions ....................................................................................................................................... 22

Electrical Specifications .................................................................................................................................. 26

Absolute Ratings ......................................................................................................................................... 26

Input/Output Capacitance .......................................................................................................................... 27

Thermal Characteristics .................................................................................................................................. 28

Electrical Specifications – I

Specifications and Conditions ............................................................................ 29

Electrical Characteristics – DDR3L (1.35V) Operating I

Specifications ........................................................... 40

Electrical Specifications – DC and AC .............................................................................................................. 43

DC Operating Conditions ........................................................................................................................... 43

Input Operating Conditions ........................................................................................................................ 44

DDR3L 1.35V AC Overshoot/Undershoot Specification ................................................................................ 48

DDR3L 1.35V Slew Rate Definitions for Single-Ended Input Signals .............................................................. 51

DDR3L 1.35V Slew Rate Definitions for Differential Input Signals ................................................................. 53

ODT Characteristics ....................................................................................................................................... 54

1.35V ODT Resistors ................................................................................................................................... 55

ODT Sensitivity .......................................................................................................................................... 56

ODT Timing Definitions ............................................................................................................................. 56

Output Driver Impedance ............................................................................................................................... 60

34 Ohm Output Driver Impedance .............................................................................................................. 61

DDR3L 34 Ohm Driver ................................................................................................................................ 62

DDR3L 34 Ohm Output Driver Sensitivity .................................................................................................... 63

DDR3L Alternative 40 Ohm Driver ............................................................................................................... 64

DDR3L 40 Ohm Output Driver Sensitivity .................................................................................................... 64

Output Characteristics and Operating Conditions ............................................................................................ 66

Reference Output Load ............................................................................................................................... 69

Slew Rate Definitions for Single-Ended Output Signals ................................................................................. 69

Slew Rate Definitions for Differential Output Signals .................................................................................... 71

Speed Bin Tables ............................................................................................................................................ 72

Electrical Characteristics and AC Operating Conditions ................................................................................... 76

Command and Address Setup, Hold, and Derating ........................................................................................... 96

Data Setup, Hold, and Derating ...................................................................................................................... 103

Commands – Truth Tables ............................................................................................................................. 111

Commands ................................................................................................................................................... 114

DESELECT ................................................................................................................................................ 114

NO OPERATION ........................................................................................................................................ 114

ZQ CALIBRATION LONG ........................................................................................................................... 114

ZQ CALIBRATION SHORT .......................................................................................................................... 114

ACTIVATE ................................................................................................................................................. 114

READ ........................................................................................................................................................ 114

WRITE ...................................................................................................................................................... 115

PRECHARGE ............................................................................................................................................. 116

REFRESH .................................................................................................................................................. 116

SELF REFRESH .......................................................................................................................................... 117

PDF: 09005aef8537e66f

4Gb_auto_DDR3L.pdf - Rev. C 2/14 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

4Gb: x8, x16 Automotive DDR3L SDRAM

Description

DLL Disable Mode ..................................................................................................................................... 118

Input Clock Frequency Change ...................................................................................................................... 122

Write Leveling ............................................................................................................................................... 124

Write Leveling Procedure ........................................................................................................................... 126

Write Leveling Mode Exit Procedure ........................................................................................................... 128

Initialization ................................................................................................................................................. 129

Voltage Initialization / Change ....................................................................................................................... 131

Voltage Switching ............................................................................................................................... 132

Mode Registers .............................................................................................................................................. 133

Mode Register 0 (MR0) ................................................................................................................................... 134

Burst Length ............................................................................................................................................. 134

Burst Type ................................................................................................................................................. 135

DLL RESET ................................................................................................................................................ 136

Write Recovery .......................................................................................................................................... 136

Precharge Power-Down (Precharge PD) ...................................................................................................... 137

CAS Latency (CL) ....................................................................................................................................... 137

Mode Register 1 (MR1) ................................................................................................................................... 138

DLL Enable/DLL Disable ........................................................................................................................... 138

Output Drive Strength ............................................................................................................................... 139

OUTPUT ENABLE/DISABLE ...................................................................................................................... 139

TDQS Enable ............................................................................................................................................. 139

On-Die Termination .................................................................................................................................. 140

WRITE LEVELING ..................................................................................................................................... 140

POSTED CAS ADDITIVE Latency ................................................................................................................ 140

Mode Register 2 (MR2) ................................................................................................................................... 141

CAS Write Latency (CWL) ........................................................................................................................... 142

AUTO SELF REFRESH (ASR) ....................................................................................................................... 142

SELF REFRESH TEMPERATURE (SRT) ........................................................................................................ 143

SRT vs. ASR ............................................................................................................................................... 143

DYNAMIC ODT ......................................................................................................................................... 143

Mode Register 3 (MR3) ................................................................................................................................... 144

MULTIPURPOSE REGISTER (MPR) ............................................................................................................ 144

MPR Functional Description ...................................................................................................................... 145

MPR Register Address Definitions and Bursting Order ................................................................................. 146

MPR Read Predefined Pattern .................................................................................................................... 152

MODE REGISTER SET (MRS) Command ........................................................................................................ 152

ZQ CALIBRATION Operation ......................................................................................................................... 153

ACTIVATE Operation ..................................................................................................................................... 154

READ Operation ............................................................................................................................................ 156

WRITE Operation .......................................................................................................................................... 167

DQ Input Timing ....................................................................................................................................... 175

PRECHARGE Operation ................................................................................................................................. 177

SELF REFRESH Operation .............................................................................................................................. 177

Extended Temperature Usage ........................................................................................................................ 179

Power-Down Mode ........................................................................................................................................ 180

RESET Operation ........................................................................................................................................... 188

On-Die Termination (ODT) ............................................................................................................................ 190

Functional Representation of ODT ............................................................................................................. 190

Nominal ODT ............................................................................................................................................ 190

Dynamic ODT ............................................................................................................................................... 192

Dynamic ODT Special Use Case ................................................................................................................. 192

Functional Description .............................................................................................................................. 192

PDF: 09005aef8537e66f

4Gb_auto_DDR3L.pdf - Rev. C 2/14 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

4Gb: x8, x16 Automotive DDR3L SDRAM

Description

Synchronous ODT Mode ................................................................................................................................ 198

ODT Latency and Posted ODT .................................................................................................................... 198

Timing Parameters .................................................................................................................................... 198

ODT Off During READs .............................................................................................................................. 201

Asynchronous ODT Mode .............................................................................................................................. 203

Synchronous to Asynchronous ODT Mode Transition (Power-Down Entry) .................................................. 205

Asynchronous to Synchronous ODT Mode Transition (Power-Down Exit) ........................................................ 207

Asynchronous to Synchronous ODT Mode Transition (Short CKE Pulse) ...................................................... 209

Revision History ............................................................................................................................................ 211

Rev. C – 02/14 ............................................................................................................................................ 211

Rev. B – 06/13 ............................................................................................................................................ 211

Rev. A – 05/13 ............................................................................................................................................ 211

PDF: 09005aef8537e66f

4Gb_auto_DDR3L.pdf - Rev. C 2/14 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

MT41K512M8RH-125AAT:E Related Products

	MT41K512M8RH-125AAT:E	MT41K512M8RH-125AIT:E	MT41K256M16HA-107AAT:E
Description	DDR DRAM, 512MX8, CMOS, PBGA78, 9 X 10.50 MM, LEAD FREE, FBGA-78	DDR DRAM, 512MX8, CMOS, PBGA78, 9 X 10.50 MM, LEAD FREE, FBGA-78	DDR DRAM, 256MX16, CMOS, PBGA96, 9 X 14 MM, LEAD FREE, FBGA-96
Maker	Micron Technology	Micron Technology	Micron Technology
package instruction	TFBGA,	TFBGA,	9 X 14 MM, LEAD FREE, FBGA-96
Reach Compliance Code	compliant	compliant	unknown
access mode	MULTI BANK PAGE BURST	MULTI BANK PAGE BURST	MULTI BANK PAGE BURST
Other features	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH
JESD-30 code	R-PBGA-B78	R-PBGA-B78	R-PBGA-B96
length	10.5 mm	10.5 mm	14 mm
memory density	4294967296 bit	4294967296 bit	4294967296 bit
Memory IC Type	DDR DRAM	DDR DRAM	DDR DRAM
memory width	8	8	16
Number of functions	1	1	1
Number of ports	1	1	1
Number of terminals	78	78	96
word count	536870912 words	536870912 words	268435456 words
character code	512000000	512000000	256000000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
organize	512MX8	512MX8	256MX16
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TFBGA	TFBGA	TFBGA
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH
Filter level	AEC-Q100	AEC-Q100	AEC-Q100
Maximum seat height	1.2 mm	1.2 mm	1.2 mm
self refresh	YES	YES	YES
Maximum supply voltage (Vsup)	1.45 V	1.45 V	1.45 V
Minimum supply voltage (Vsup)	1.283 V	1.283 V	1.283 V
Nominal supply voltage (Vsup)	1.35 V	1.35 V	1.35 V
surface mount	YES	YES	YES
technology	CMOS	CMOS	CMOS
Terminal form	BALL	BALL	BALL
Terminal pitch	0.8 mm	0.8 mm	0.8 mm
Terminal location	BOTTOM	BOTTOM	BOTTOM
width	9 mm	9 mm	9 mm
Base Number Matches	1	1	-

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