K4J52324QC
512M GDDR3 SDRAM
512Mbit GDDR3 SDRAM
Revision 1.5
June 2006
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
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Rev. 1.5 June 2006
K4J52324QC
Revision History
Revision 1.5 (June 29, 2006)
•.Added comment on page 28.
512M GDDR3 SDRAM
Revision 1.4 (March 22, 2006)
•.Added CKE condition in Intialization Sequence #4 on page 10.
• Changed minimum delay from a read w/AP to write or write w/AP on page 50.
Revision 1.3 (November 4, 2005)
• Changed tRFC of -BC16 from 33tCK to 31tCK effective date code with WW0543.
• Typo corrected on page 4.
Revision 1.2 (September 26, 2005)
• Redefined -BJ11’s AC core spec parameters. Refer to the AC characteristics table on page 56.
• Added current spec of -BJ11
• IBIS curve added.
• ICC6 changed from 50mA to 35mA for -BC** starting from Sep’01
Revision 1.1 (August 8, 2005)
• Removed -BJ14 from the spec.
• Added -BJ11 as a preliminary spec. Accordingly, CL12 added as well.
• Removed additive latency (AL) from the spec.
• Minor changes : Corrected typo on page 17, data driver impedance. Note 9 added on page 51. Added supplementary explanation on
VDD&VDDQ=2.0V operation on page 51and 52.
• Removed tFAW restriction on -BJ** part only. All -BC** part should follow tFAW spec.
• Added tXSNR on page 56.
Revision 1.0 (March 8, 2005)
• Removed -BC10/11/12 from the spec.
• Separated VDD spec as below
- VDD & VDDQ = 2.0V + 0.1V distinguished by part number as -BJ
- VDD & VDDQ = 1.8V + 0.1V distinguished by part number as -BC
Accordingly, defined -BJ12/14 and -BC14/16/20 along with supported operating voltage.
• Changed tRCDR and tRP of -BC16 from 9tCK and 8tCK to 10tCK and 9tCK. Accordingly, tRCDW/tRC/tDAL changed each from 5tCK/
27tCK/17tCK to 6tCK/28tCK/18tCK.
• Changed tRCDR and tRP of -BC20 from 7tCK and 6tCK to 8tCK and 7tCK. Accordingly, tRCDW/tRC/tDAL changed each from 4tCK/
21tCK/13tCK to 5tCK/22tCK/14tCK.
• Added Vendor ID read timing on page 18 & clock frequency change timing on page 19.
• Changed package dimension from 12mm x 14mm to 11mm x 14mm.
• DC spec updated.
• Capacitance values changed. Input(Clock,Address,Command) capacitance changed from 2.0pF/2.5pF to 1.5pF/3.0pF and DQ,DQS
and DM capacitance changed from 2.0pF/2.5pF to 1.5pF/2.0pF.
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Rev. 1.5 June 2006
K4J52324QC
Revision History
Revision 0.9 (November 11, 2004)
• Corrected typo in boundary scan order table.
512M GDDR3 SDRAM
Revision 0.8 (October 10, 2004)
• Changed part number from K4J52324QB-G to K4J52324QC-B
-Package code attribute re-defined : G .... 144FBGA, Leaded V .... 144FBGA, Lead-free
A .... 136FBGA, Leaded
B .... 136FBGA, Lead-free
Revision 0.7 (October 5, 2004)
• DC spec defined.
• Comment added on how to change the clock frequency after the power-up (page 14)
• Comment added on read to write timing diagram on page 32 which specify the timing interval from data termination enable to the first
data-in should be greater than 1tCK.
• Changed CL(Cas Latency) of -GC14 from 9tCK to 10tCK . Changed CL(Cas Latency) of -GC16 from 8tCK to 9tCK
• Typo corrected in boundary scan order table and additional remark for boundary scan added on page 17.
• Changed tDCERR from 0.2tCK to 0.03tCK (Typo)
Revision 0.6 (September 15, 2004)
• Typo corrected
• Removed tWR_A to avoid confusion. Instead, tWR represent write recovery time for both normal precharge and Auto-precharge cases.
Accordingly tDAL adjusted by tWR for each frequency.
• Clock jitter spec added.
• Changed input capacitance.
• Fixed CL of -GC12 to 11tCK where as specified with 10tCK or 11tCK previously.
Revision 0.5 (June 4, 2004)
• Typo corrected (Package ball out)
Revision 0.4 (May 13, 2004)
• Changed tRRD from 12ns to 10ns
• Added tFAW specification in the spec which defined as five times of tRRD
• Added boundary scan specification & added package dimension
Revision 0.3 (January 26, 2004)
• Changed part number of 512Mb(x32) GDDR3 from K4J53324QB-GC to K4J52324QB-GC
Revision 0.2 (January 5, 2004)
• Added Write Latency 5, 6, and 7 (clock) in the spec.
• Added tWR_A 8 and 9 (clock) in the spec.
Revision 0.1 (December 18, 2003)
• Changed CL of -GC12 from 9tCK to 10tCK
• Changed tCK(max) from 3.0ns to 3.3ns
Revision 0.0 (December 18 , 2003) -
Target Spec
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Rev. 1.5 June 2006
K4J52324QC
512M GDDR3 SDRAM
2M x 32Bit x 8 Banks Graphic Double Data Rate 3 Synchronous DRAM
with Uni-directional Data Strobe
FEATURES
• 2.0V + 0.1V power supply for device operation for -BJ**
• 2.0V + 0.1V power supply for I/O interface for -BJ**
• 1.8V + 0.1V power supply for device operation for -BC**
• 1.8V + 0.1V power supply for I/O interface for -BC**
• On-Die Termination (ODT)
• Output Driver Strength adjustment by EMRS
• Calibrated output drive
• 1.8V Pseudo Open drain compatible inputs/outputs
• 8 internal banks for concurrent operation
• Differential clock inputs (CK and CK)
• Commands entered on each positive CK edge
• CAS latency : 4, 5, 6, 7, 8, 9, 10, 11, 12 (clock)
• Programmable Burst length : 4 and 8
• Single ended READ strobe (RDQS) per byte
• Single ended WRITE strobe (WDQS) per byte
• RDQS edge-aligned with data for READs
• WDQS center-aligned with data for WRITEs
• Data Mask(DM) for masking WRITE data
• Auto & Self refresh modes
• Auto Precharge option
• 32ms, auto refresh (8K cycle)
• 136 Ball FBGA
• Maximum clock frequency up to 900MHz
• Maximum data rate up to 1.8Gbps/pin
• DLL for outputs
• Boundary scan function with SEN pin
• Programmable Write latency : 1, 2, 3, 4, 5, 6 and 7 (clock) • Mirror function with MF pin
ORDERING INFORMATION
Part NO.
K4J52324QC-BJ11
K4J52324QC-BJ12
K4J52324QC-BC14
K4J52324QC-BC16
K4J52324QC-BC20
Max Freq.
900MHz
800MHz
700MHz
600MHz
500MHz
Max Data Rate
1.8Gbps/pin
1.6Gbps/pin
1.4Gbps/pin
1.2Gbps/pin
1.0Gbps/pin
1.8V+0.1V
VDD&VDDQ
2.0V+0.1V
136 Ball FBGA
Package
K4J52324QC-A*** is leaded package part number
GENERAL DESCRIPTION
FOR 2M x 32Bit x 8 Bank GDDR3 SDRAM
The K4J52324QC is 536,870,912 bits of hyper synchronous data rate Dynamic RAM organized as 8 x 2,097,152 words by
32 bits, fabricated with SAMSUNG
’s
high performance CMOS technology. Synchronous features with Data Strobe allow
extremely high performance up to 7.2GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of
operating frequencies, and programmable latencies allow the device to be useful for a variety of high performance memory
system applications.
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Rev. 1.5 June 2006
K4J52324QC
PIN CONFIGURATION
Normal Package (Top View)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
V
VDDQ
VSSQ
VDDQ
VSSQ
VDDQ
VDD
VSS
VREF
VSSA
VDDA
VSS
VDD
VDDQ
VSSQ
VDDQ
VSSQ
VDDQ
2
VDD
DQ0
DQ2
WDQS0
DQ4
DQ6
VSSQ
A1
RFU1
A10
VSSQ
DQ24
DQ26
WDQS3
DQ28
DQ30
VDD
3
VSS
DQ1
DQ3
RDQS0
DM0
DQ5
DQ7
RAS
RFU2
A2
DQ25
DQ27
DM3
RDQS3
DQ29
DQ31
VSS
4
ZQ
VSSQ
VDDQ
VSSQ
VDDQ
CAS
BA0
CKE
VDDQ
A0
A11
A3
VDDQ
VSSQ
VDDQ
VSSQ
SEN
5
6
7
8
9
MF
VSSQ
VDDQ
VSSQ
VDDQ
CS
BA1
WE
VDDQ
A4
A7
A9
VDDQ
VSSQ
VDDQ
VSSQ
RESET
512M GDDR3 SDRAM
10
VSS
DQ9
DQ11
RDQS1
DM1
DQ13
DQ15
BA2
CK
A6
DQ17
DQ19
DM2
RDQS2
DQ21
DQ23
VSS
11
VDD
DQ8
DQ10
WDQS1
DQ12
DQ14
VSSQ
A5
CK
A8/AP
VSSQ
DQ16
DQ18
WDQS2
DQ20
DQ22
VDD
12
VDDQ
VSSQ
VDDQ
VSSQ
VDDQ
VDD
VSS
VREF
VSSA
VDDA
VSS
VDD
VDDQ
VSSQ
VDDQ
VSSQ
VDDQ
NOTE :
1. RFU1 is reserved for future use
2. RFU2 is reserved for future use
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Rev. 1.5 June 2006
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