530KB622M080BGR datasheet, PDF

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530KB622M080BGR: DescriptionCML Output Clock Oscillator; CategoryPassive components oscillator; File Size171KB，10 Pages; ManufacturerSilicon Laboratories Inc

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530KB622M080BGR Overview

CML Output Clock Oscillator

530KB622M080BGR Parametric

Parameter Name	Attribute value
Reach Compliance Code	unknown
Manufacturer's serial number	SI530
Oscillator type	CML
Base Number Matches	1

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S i 5 3 0 / 5 31

R E L I M I N A R Y

A TA

H E E T

R Y S TA L

S C I L L A T O R

(XO)

(10 M H

Z T O

1.4 G H

)

Features

Available with any-rate output

frequencies from 10 MHz to 945 MHz

and select frequencies to 1.4 GHz

3rd generation DSPLL

with superior

jitter performance

3x better frequency stability than

SAW-based oscillators

Internal fixed crystal frequency

ensures high reliability and low

aging

Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

Pb-free/RoHS-compliant

Si5602

Ordering Information:

See page 6.

Applications

SONET/SDH

Networking

SD/HD video

Clock and data recovery

FPGA/ASIC clock generation

Pin Assignments:

See page 5.

(Top View)

GND

Description

The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry

to provide a low jitter clock at high frequencies. The Si530/531 is available

with any-rate output frequency from 10 to 945 MHz and select frequencies to

1400 MHz. Unlike a traditional XO, where a different crystal is required for

each output frequency, the Si530/531 uses one fixed crystal to provide a

wide range of output frequencies. This IC based approach allows the crystal

resonator to provide exceptional frequency stability and reliability. In addition,

DSPLL clock synthesis provides superior supply noise rejection, simplifying

the task of generating low jitter clocks in noisy environments typically found in

communication systems. The Si530/531 IC based XO is factory configurable

for a wide variety of user specifications including frequency, supply voltage,

output format, and temperature stability. Specific configurations are factory

programmed at time of shipment, thereby eliminating long lead times

associated with custom oscillators.

CLK–

CLK+

Si530 (LVDS/LVPECL/CML)

GND

Functional Block Diagram

CLK– CLK+

CLK+

Si530 (CMOS)

Fixed

Frequency

Any-rate

10–1400 MHz

DSPLL®

Clock

Synthesis

GND

CLK–

CLK+

Si531 (LVDS/LVPECL/CML)

GND

Preliminary Rev. 0.4 5/06

Si530/531

This information applies to a product under development. Its characteristics and specifications are subject to change without notice.

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