Am29SL800D
Data Sheet
July 2003
The following document specifies Spansion memory products that are now offered by both Advanced
Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig-
inally developed the specification, these products will be offered to customers of both AMD and
Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal datasheet improvement and are noted in the
document revision summary, where supported. Future routine revisions will occur when appropriate,
and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM.” To order
these products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about Spansion
memory solutions.
Publication Number
27546
Revision
E
Publication Number 27546 Revision
A
Amendment
+3
Issue Date
November 2, 2004
Amendment
+3 Issue Date
November 2, 2004
THIS PAGE LEFT INTENTIONALLY BLANK.
2
Am29SL800D
November 2, 2004
Am29SL800D
8 Megabit (1 M x 8-Bit/512 K x 16-Bit)
CMOS 1.8 Volt-only Super Low Voltage Flash Memory
DISTINCTIVE CHARACTERISTICS
Single power supply operation
— 1.65 to 2.2 V for read, program, and erase
operations
— Ideal for battery-powered applications
Manufactured on 0.23 µm process technology
— Compatible with 0.32 µm Am29SL800C device
High performance
— Access times as fast as 90 ns
Ultra low power consumption (typical values at 5
MHz)
— 0.2 µA Automatic Sleep Mode current
— 0.2 µA standby mode current
— 5 mA read current
— 15 mA program/erase current
Flexible sector architecture
— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and
fifteen 64 Kbyte sectors (byte mode)
— One 8 Kword, two 4 Kword, one 16 Kword, and
fifteen 32 Kword sectors (word mode)
— Supports full chip erase
— Sector Protection features:
A hardware method of locking a sector to prevent
any program or erase operations within that
sector
Sectors can be locked in-system or via
programming equipment
Temporary Sector Unprotect feature allows code
changes in previously locked sectors
Unlock Bypass Program Command
— Reduces overall programming time when issuing
multiple program command sequences
Top or bottom boot block configurations
available
Embedded AlgorithmsNov 2, 2004
— Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
— Embedded Program algorithm automatically
writes and verifies data at specified addresses
Minimum 1,000,000 erase cycle guarantee per
sector
20-year data retention at 125
°
C
Package option
— 48-pin TSOP
— 48-ball FBGA
Compatibility with JEDEC standards
— Pinout and software compatible with single-
power supply Flash
— Superior inadvertent write protection
Data# Polling and toggle bits
— Provides a software method of detecting program
or erase operation completion
Ready/Busy# pin (RY/BY#)
— Provides a hardware method of detecting
program or erase cycle completion
Erase Suspend/Erase Resume
— Suspends an erase operation to read data from,
or program data to, a sector that is not being
erased, then resumes the erase operation
Hardware reset pin (RESET#)
— Hardware method to reset the device to reading
array data
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice.
Publication#
27546
Rev:
E
Amendment/3
Issue Date:
Nov 2, 2004
Refer to AMD’s Website (www.amd.com) for the latest information
D A T A S H E E T
GENERAL DESCRIPTION
The Am29SL800D is an 8 Mbit, 1.8 V volt-only Flash
memory organized as 1,048,576 bytes or 524,288
words. The device is offered in 48-pin TSOP and 48-
ball FBGA packages. The word-wide data (x16)
appears on DQ15–DQ0; the byte-wide (x8) data
appears on DQ7–DQ0. This device is designed to be
programmed and erased in-system with a single 1.8
volt V
CC
supply. No V
PP
is for write or erase operations.
The device can also be programmed in standard
EPROM programmers.
The standard device offers access times of 90, 100,
120, and 150 ns, allowing high speed microprocessors
to operate without wait states. To eliminate bus conten-
tion the device has separate chip enable (CE#), write
enable (WE#) and output enable (OE#) controls.
The device requires only a
single 1.8 volt power
supply
for both read and write functions. Internally
generated and regulated voltages are provided for the
program and erase operations.
The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard.
Com-
mands are written to the command register using
standard microprocessor write timings. Register con-
tents serve as input to an internal state-machine that
controls the erase and programming circuitry. Write
cycles also internally latch addresses and data needed
for the programming and erase operations. Reading
data out of the device is similar to reading from other
Flash or EPROM devices.
Device programming occurs by executing the program
command sequence. This initiates the
Embedded
Program
algorithm—an internal algorithm that auto-
matically times the program pulse widths and verifies
proper cell margin. The
Unlock Bypass
mode facili-
tates faster programming times by requiring only two
write cycles to program data instead of four.
Device erasure occurs by executing the erase
command sequence. This initiates the
Embedded
Erase
algorithm—an internal algorithm that automati-
cally preprograms the array (if it is not already
programmed) before executing the erase operation.
During erase, the device automatically times the erase
pulse widths and verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, or by reading the DQ7 (Data# Polling) and DQ6
(toggle)
status bits.
After a program or erase cycle has
been completed, the device is ready to read array data
or accept another command.
The
sector erase architecture
allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection
measures include a low
V
CC
detector that automatically inhibits write opera-
tions during power transitions. The
hardware sector
protection
feature disables both program and erase
operations in any combination of the sectors of
memory. This can be achieved in-system or via pro-
gramming equipment.
The
Erase Suspend
feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector that is not selected for
erasure. True background erase can thus be achieved.
The
hardware RESET# pin
terminates any operation
in progress and resets the internal state machine to
reading array data. The RESET# pin may be tied to the
system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor
to read the boot-up firmware from the Flash memory.
The device offers two power-saving features. When
addresses have been stable for a specified amount of
time, the device enters the
automatic sleep mode.
The system can also place the device into the
standby
mode.
Power consumption is greatly reduced in both
these modes.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effectiveness.
The device electrically erases all bits within a sector
simultaneously via Fowler-Nordheim tunneling. The
data is programmed using hot electron injection.
2
Am29SL800D
Nov 2, 2004
D A T A S H E E T
TABLE OF CONTENTS
General Description . . . . . . . . . . . . . . . . . . . . . . . . 2
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 5
Special Handling Instructions for FBGA Packages .................. 6
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 8
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 10
Table 1. Am29SL800D Device Bus Operations ..............................10
DQ5: Exceeded Timing Limits ................................................ 23
DQ3: Sector Erase Timer ....................................................... 23
Table 6. Write Operation Status ..................................................... 24
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 25
Figure 7. Maximum Negative Overshoot Waveform Maximum Nega-
tive Overshoot Waveform............................................................... 25
Figure 8. Maximum Positive Overshoot Waveform........................ 25
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 25
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 9. I
CC1
Current vs. Time (Showing Active and Automatic
Sleep Currents) .............................................................................. 27
Figure 10. Typical I
CC1
vs. Frequency ........................................... 27
Word/Byte Configuration ........................................................ 10
Requirements for Reading Array Data ................................... 10
Writing Commands/Command Sequences ............................ 10
Program and Erase Operation Status .................................... 11
Standby Mode ........................................................................ 11
Automatic Sleep Mode ........................................................... 11
RESET#: Hardware Reset Pin ............................................... 11
Output Disable Mode .............................................................. 12
Table 2. Am29SL800DT Top Boot Block Sector Address Table .....12
Table 3. Am29SL800DB Bottom Boot Block Sector Address Table 13
Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 11. Test Setup..................................................................... 28
Table 7. Test Specifications ........................................................... 28
Key to Switching Waveforms .................................................. 28
Figure 12. Input Waveforms and Measurement Levels ................. 28
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 29
Read Operations .................................................................... 29
Figure 13. Read Operations Timings ............................................. 29
Figure 14. RESET# Timings .......................................................... 30
Autoselect Mode ..................................................................... 14
Table 4. Am29SL800D Autoselect Codes (High Voltage Method) ..14
Word/Byte Configuration (BYTE#) ........................................ 31
Figure 15. BYTE# Timings for Read Operations............................ 31
Figure 16. BYTE# Timings for Write Operations............................ 31
Sector Protection/Unprotection ............................................... 14
Temporary Sector Unprotect .................................................. 14
Figure 1. In-System Sector Protect/Unprotect Algorithms .............. 15
Figure 2. Temporary Sector Unprotect Operation........................... 16
Erase/Program Operations ..................................................... 32
Figure 17. Program Operation Timings..........................................
Figure 18. Chip/Sector Erase Operation Timings ..........................
Figure 19. Data# Polling Timings (During Embedded Algorithms).
Figure 20. Toggle Bit Timings (During Embedded Algorithms)......
Figure 21. DQ2 vs. DQ6.................................................................
33
34
35
35
36
Hardware Data Protection ...................................................... 16
Low V
CC
Write Inhibit .............................................................. 16
Write Pulse “Glitch” Protection ............................................... 16
Logical Inhibit .......................................................................... 16
Power-Up Write Inhibit ............................................................ 16
Command Definitions . . . . . . . . . . . . . . . . . . . . . 16
Reading Array Data ................................................................ 16
Reset Command ..................................................................... 16
Autoselect Command Sequence ............................................ 17
Word/Byte Program Command Sequence ............................. 17
Unlock Bypass Command Sequence ..................................... 17
Figure 3. Program Operation .......................................................... 18
Temporary Sector Unprotect .................................................. 36
Figure 22. Temporary Sector Unprotect Timing Diagram .............. 36
Figure 23. Sector Protect/Unprotect Timing Diagram .................... 37
Alternate CE# Controlled Erase/Program Operations ............ 38
Figure 24. Alternate CE# Controlled Write Operation Timings ...... 39
Chip Erase Command Sequence ........................................... 18
Sector Erase Command Sequence ........................................ 18
Erase Suspend/Erase Resume Commands ........................... 19
Figure 4. Erase Operation............................................................... 19
Table 5. Am29SL800D Command Definitions ................................20
Write Operation Status . . . . . . . . . . . . . . . . . . . . 21
DQ7: Data# Polling ................................................................. 21
Figure 5. Data# Polling Algorithm ................................................... 21
RY/BY#: Ready/Busy# ........................................................... 22
DQ6: Toggle Bit I .................................................................... 22
DQ2: Toggle Bit II ................................................................... 22
Reading Toggle Bits DQ6/DQ2 .............................................. 22
Figure 6. Toggle Bit Algorithm......................................................... 23
Erase and Programming Performance . . . . . . . 40
Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 40
TSOP Pin Capacitance . . . . . . . . . . . . . . . . . . . . . 40
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 41
TS 048–48-Pin Standard TSOP ............................................. 41
TSR048–48-Pin Reverse TSOP ............................................. 42
FBA048–48-Ball Fine-Pitch Ball Grid Array (FBGA)
6 x 8 mm package .................................................................. 43
FBC048–48-Ball Fine-Pitch Ball Grid Array (FBGA)
8 x 9 mm package .................................................................. 44
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 45
Revision A (February 4, 2003) ................................................ 45
Revision A+1 (March 17, 2003) .............................................. 45
Revision A+2 (June 10, 2004) ................................................ 45
Revision A+3 (October 27, 2004) ........................................... 45
Nov 2, 2004
Am29SL800D
3
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