530KC1338M00DG datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > Passive components> oscillator> 530KC1338M00DG

530KC1338M00DG: DescriptionCMOS/TTL Output Clock Oscillator, 1338MHz Nom, ROHS COMPLIANT, SMD, 6 PIN; CategoryPassive components oscillator; File Size215KB，12 Pages; ManufacturerSilicon Laboratories Inc; Environmental Compliance

Download Datasheet Parametric View All

530KC1338M00DG Overview

CMOS/TTL Output Clock Oscillator, 1338MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

530KC1338M00DG Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
package instruction	ROHS COMPLIANT, SMD, 6 PIN
Reach Compliance Code	unknown
Is Samacsys	N
Other features	TRAY
maximum descent time	0.35 ns
Frequency Adjustment - Mechanical	NO
frequency stability	7%
JESD-609 code	e4
Manufacturer's serial number	530
Installation features	SURFACE MOUNT
Nominal operating frequency	1338 MHz
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Oscillator type	CMOS/TTL
physical size	7.0mm x 5.0mm x 1.85mm
longest rise time	0.35 ns
Maximum supply voltage	1.89 V
Minimum supply voltage	1.71 V
Nominal supply voltage	1.8 V
surface mount	YES
maximum symmetry	55/45 %
Terminal surface	Nickel/Gold (Ni/Au)
Base Number Matches	1

Preview

Download Datasheet

View All

S i 5 3 0 / 5 31

EVISION

R Y S TA L

S C I L L A T O R

(XO)

(10 M H

Z T O

1.4 G H

)

Features

Available with any-rate output

frequencies from 10 MHz to 945 MHz

and select frequencies to 1.4 GHz

3rd generation DSPLL

with superior

jitter performance

3x better frequency stability than

SAW-based oscillators

Internal fixed crystal frequency

ensures high reliability and low

aging

Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

Pb-free/RoHS-compliant

Si5602

Ordering Information:

See page 7.

Applications

SONET/SDH

Networking

SD/HD video

Test and measurement

Clock and data recovery

FPGA/ASIC clock generation

Pin Assignments:

See page 6.

(Top View)

GND

Description

The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry

to provide a low jitter clock at high frequencies. The Si530/531 is available

with any-rate output frequency from 10 to 945 MHz and select frequencies to

1400 MHz. Unlike a traditional XO, where a different crystal is required for

each output frequency, the Si530/531 uses one fixed crystal to provide a

wide range of output frequencies. This IC based approach allows the crystal

resonator to provide exceptional frequency stability and reliability. In addition,

DSPLL clock synthesis provides superior supply noise rejection, simplifying

the task of generating low jitter clocks in noisy environments typically found in

communication systems. The Si530/531 IC based XO is factory configurable

for a wide variety of user specifications including frequency, supply voltage,

output format, and temperature stability. Specific configurations are factory

programmed at time of shipment, thereby eliminating long lead times

associated with custom oscillators.

CLK–

CLK+

Si530 (LVDS/LVPECL/CML)

GND

Functional Block Diagram

CLK– CLK+

CLK

Si530 (CMOS)

Fixed

Frequency

Any-rate

10–1400 MHz

DSPLL

Clock

Synthesis

GND

CLK–

CLK+

Si531 (LVDS/LVPECL/CML)

GND

Rev. 1.1 6/07

Si530/531

Recommended Resources

MM36SB020 two-wire wiring circuit diagram

Dongpeng P300 power amplifier circuit

LT1086 application circuit diagram

Signaling to the control room using a single wire

TDA7050T power amplifier circuit

14. Power supply circuit diagram of AST MPX-2 color display

[Serial] [ALIENTEK Battleship STM32 Development Board] STM32 Development Guide--Chapter 9 Serial Port Experiment: [align=left][b]Chapter 9 Serial Port Experiment[/b] The previous two chapters introduced the IO port operation of STM32. In this chapter, we will learn about the serial port of STM32 and teach you how...; 正点原子 stm32/stm8

I have run 58 kilometers this month, keep it up!: ...; chenzhufly Talking

HIVE+binfs how to save the registry, the code has been modified, but the function can not be realized, please give me some advice: : According to the relevant information available on the Internet, I have made some modifications. The Hive-base option has been added, and the platform.reg file has been modified accordingly. The fol...; guoqingling988 Embedded System

[Design Tools] 5-hour FPGA PCIE design tutorial for beginners: In recent years, as FPGAs have become increasingly powerful, many high-speed designs have begun to use FPGAs to implement high-speed serial protocols such as PCIE. RD products need to be considered fr...; GONGHCU FPGA/CPLD

About the PWM waveform distortion of DSP2812: The PWM waveform I measured with an oscilloscope has very slow rising and falling edges.Uploaded 2 hours agoDownload attachment(43.95 KB)I measured the square wave from the signal generator... the wav...; foreverlove3721 Microcontroller MCU

Under what circumstances will it enter: MemManageException: I often get MemManageException when debugging the file system recently. I have no idea what to do now. Please give me some advice....; lingd stm32/stm8

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components