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Stratix V Device Handbook
Volume 1: Overview and Datasheet
February 2012
Subscribe
1–2
Chapter 1: Stratix V Device Family Overview
Stratix V Family Variants
Stratix V E
devices offer the highest logic density within the Stratix V family with
nearly one million logic elements (LEs) in the largest device. These devices are
optimized for applications such as ASIC and system emulation, diagnostic imaging,
and instrumentation.
Common to all Stratix V family variants are a rich set of high-performance building
blocks, including a redesigned adaptive logic module (ALM), 20 Kbit (M20K)
embedded memory blocks, variable precision DSP blocks, and fractional
phase-locked loops (PLLs). All of these building blocks are interconnected by Altera’s
superior multi-track routing architecture and comprehensive fabric clocking network.
Also common to Stratix V devices is the new Embedded HardCopy Block, which is a
customizable hard IP block that leverages Altera’s unique HardCopy ASIC
capabilities. The Embedded HardCopy Block in Stratix V FPGAs is used to harden IP
instantiation of PCIe Gen3, Gen2, and Gen1.
Stratix V Device Handbook
Volume 1: Overview and Datasheet
February 2012 Altera Corporation
Chapter 1: Stratix V Device Family Overview
Stratix V Features Summary
1–3
Stratix V Features Summary
■
Technology
■
■
■
Embedded memory blocks
■
■
28-nm TSMC process technology
0.85-V core voltage
■
M20K: 20-Kbit with hard error correction code (ECC)
MLAB: 640-bit
Up to 500 MHz performance
Natively support signal processing with precision
ranging from 9x9 up to 54x54
New native 27x27 multiply mode
64-bit accumulator and cascade for systolic finite
impulse responses (FIRs)
Embedded internal coefficient memory
Pre-adder/subtractor improves efficiency
Increased number of outputs allows more independent
1. Check the data sheet:1. Sending mode: Send slave address: 0x23, send instruction 0x10; end;
Wait 180ms for data collection;
2. Receiving mode: Send slave address: 0x23, wait for high byte data from...
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