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DS2176
T1 Receive Buffer
www.dalsemi.com
FEATURES
§
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§
§
§
§
§
§
§
§
§
PIN ASSIGNMENT
SIGH
RMSYN
RCLK
RSER
A
B
C
D
SCHCLK
SM0
SM1
VSS
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VDD
SCKLSEL
SYCLK
SSER
SLIP
SBIT8
SMSYNC
SIGFRZ
SFSYNC
ALN
FMS
S/P
Synchronizes loop–timed and system–timed
T1 data streams
Two–frame buffer depth; slips occur on frame
boundaries
Output indicates when slip occurs
Buffer may be recentered externally
Ideal for 1.544 to 2.048 MHz rate conversion
Interfaces to parallel or serial backplanes
Extracts and buffers robbed–bit signaling
Inhibits signaling updates during alarm or slip
conditions
Integration feature “debounces” signaling
Slip–compensated output indicates when
signaling updates occur
Compatible with DS2180A T1 Transceiver
Surface mount package available, designated
DS2176Q
Industrial temperature range of –40°C to
+85°C available, designated DS2176N
24-PIN 300 MIL DIP
A
B
NC
NC
C
D
SCHCLK
RSER
RCLK
RMSYNC
SIGH
VDD
SCKLSEL
SYSCLK
4
5
6
7
8
9
10
11
12
13 14
15
16
17
18
3
2
1
28
27
26
25
24
23
22
21
20
19
SSER
SLIP
SBIT8
NC
NC
SMSYNC
SIGFRZ
DESCRIPTION
The DS2176 is a low–power CMOS device specifically designed for synchronizing receive side loop–
timed T–carrier data streams with system side timing. The device has several flexible operating modes
which simplify interfacing incoming data to parallel and serial TDM backplanes. The device extracts,
buffers and integrates ABCD signaling; signaling updates are prohibited during alarm or slip conditions.
The buffer replaces extensive hardware in existing applications with one “skinny” 24–lead package.
Application areas include digital trunks, drop and insert equipment, transcoders, digital cross–connects
(DACS), private network equipment and PABX–to–computer interfaces such as DMI and CPI.
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091599
SM0
SM1
VSS
S/P
FMS
ALN
SFSYNC
28-PIN PLCC
DS2176
DS2176 BLOCK DIAGRAM Figure 1
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DS2176
PIN DESCRIPTION Table 1
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
SYMBOL
SIGN
RMSYNC
RCLK
RSER
A
B
C
D
SCHCLK
SM0
SM1
V
SS
S/
P
FMS
TYPE
I
I
I
I
O
DESCRIPTION
Signaling Inhibit.
When low, ABCD signaling updates are disabled for
a period determined by SM0 and SM1, or until returned high.
Receive Multifram Sync.
Must be pulsed high at multiframe
boundaries to establish frame and multiframe alignment.
Receive Clock.
Primary 1.544 MHz clock.
Receive Serial Data.
Sampled on Falling edge of RCLK.
Robbed-Bit Signaling Outputs.
O
I
–
I
I
I
I
O
O
O
O
O
I
I
–
System Channel Clock.
Transitions high on channel boundaries; useful
for serial to parallel conversion of channel data.
Signaling Modes 0 and 1.
Select signaling supervision technique.
Signal Ground.
0.0 volts.
Serial/Parallel Select.
Tie to V
SS
for parallel backplane applications, to
V
DD
for serial.
Frame Mode Select.
Tie to V
SS
to select 193S(D4) framing to V
DD
for
193E (extended).
Align.
Recenters buffer on next system side frame boundary when
forced low.
System Frame Sync.
Rising edge establishes start of frame.
Signaling Freeze.
When high, indicates signaling updates have been
disabled internally via a slip or externally by forcing
SIGH
low.
System Multiframe Sync.
Slip-compensated multiframe output;
indicates when signaling updates are made.
System Bit 8.
High during the LSB time of each channel. Used to
reinsert extracted signaling into outgoing data stream.
Frame Slip.
Active low, open collector output. Held low for 65
SYSCLK cycles when a slip occurs.
System Serial Out.
Updated on rising edge of SYSCLK.
System Clock. 1.544 or 2.048 MHz data clock.
System Clock Select.
Tie to V
SS
for 1.544 MHz applications, to V
DD
for
2.048 MHz.
Positive Supply.
5.0 volts.
ALN
SFSYNC
SIGFRZ
SMSYNC
SBIT8
SLIP
SSER
SYSCLK
SCLKSEL
V
DD
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DS2176
OVERVIEW
The DS2176 performs two primary functions: 1) synchronization of received T1 PCM data (looped
timed) to host backplane frequencies; 2) supervision of robbed–bit signaling data embedded in the data
stream. The buffer, while optimized for use with the DS2180A T1 Transceiver, is also compatible with
other transceiver devices. The DS2180A data sheet should serve as a valuable reference when designing
with the DS2176.
RECEIVE SIDE TIMING FIGURE 2
DATA SYNCHRONIZATION
PCM BUFFER
The DS2176 utilizes a 2–frame buffer (386 bits) to synchronize incoming PCM data to the system
backplane clock. The buffer samples data at RSER on the falling edge of RCLK. Output data appears at
SSER and is up-dated on the rising edge of SYSCLK. A rising edge at RMSYNC establishes receive side
frame and multi-frame alignment. A rising edge at SFSYNC establishes system side frame alignment.
The buffer depth is constantly monitored by onboard contention logic; a “slip” occurs when the buffer is
completely emptied or filled. Slips automatically recenter the buffer to a one–frame depth and always
occur on frame boundaries.
SLIP CORRECTION CAPABILITY
The 2–frame buffer depth is adequate for most T–carrier applications where short–term jitter
synchronization, rather than correction of significant frequency differences, is required. The DS2176
provides an ideal balance between total delay and slip correction capability.
BUFFER RECENTERING
Many applications require that the buffer be recentered during system power–up and/or initialization.
Forcing
ALN
low recenters the buffer on the occurrence of the next frame sync boundary. A slip will
occur during this recentering if the buffer depth is adjusted. If the depth is presently optimum, no
adjustment (slip) occurs.
SLIP
is held low for 65 SYSCLK cycles when a slip occurs.
SLIP
is an active–
low, open collector output.
BUFFER DEPTH MONITORING
SMSYNC is a system side output pulse which indicates system side multiframe boundaries. The distance
between rising edges at RMSYNC and SMSYNC indicates the current buffer depth. Slip direction and/or
an impending slip condition may be determined by monitoring RMSYNC and SMSYNC real time.
SMSYNC is held high for 65 SYSCLK cycles.
CLOCK SELECT
The device is compatible with two common backplane frequencies: 1.544 MHz, selected when
SCLKSEL=0; and 2.048 MHz, selected when SCLKSEL=1. In 1.544 MHz applications the F–bit is
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