GC80960RN100 datasheet, PDF - EEWORLD Datasheet

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GC80960RN100: DescriptionRISC Microprocessor, 32-Bit, 100MHz, CMOS, PBGA540, PLASTIC, BGA-540; CategoryThe embedded processor and controller Microcontrollers and processors; File Size394KB，54 Pages; ManufacturerIntel; Websitehttp://www.intel.com/

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GC80960RN100 Overview

RISC Microprocessor, 32-Bit, 100MHz, CMOS, PBGA540, PLASTIC, BGA-540

GC80960RN100 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Intel
Parts packaging code	BGA
package instruction	BGA, BGA540,32X32,50
Contacts	540
Reach Compliance Code	unknown
ECCN code	3A991.A.2
Other features	OPERATING CASE TEMPERATURE 0 TO 90
Address bus width	32
bit size	32
boundary scan	YES
maximum clock frequency	33.33 MHz
External data bus width	32
Format	FIXED POINT
Integrated cache	YES
JESD-30 code	S-PBGA-B540
JESD-609 code	e0
length	42.5 mm
low power mode	YES
Number of terminals	540
Maximum operating temperature	85 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Encapsulate equivalent code	BGA540,32X32,50
Package shape	SQUARE
Package form	GRID ARRAY
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	3.3,3.3/5 V
Certification status	Not Qualified
Maximum seat height	4.1 mm
speed	100 MHz
Maximum slew rate	1650 mA
Maximum supply voltage	3.6 V
Minimum supply voltage	3 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Temperature level	OTHER
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	42.5 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR, RISC
Base Number Matches	1

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Intel

80960RN I/O Processor

Complies with PCI Local Bus Specification, Revision 2.2

Universal (5 V and 3.3 V) PCI Signalling Environment (C-stepping only)

Data Sheet

Product Features

High Performance Intel

80960JT Core

—Sustained One Instruction/Clock Execution

— 16 Kbyte, Two-Way Set-Associative

Instruction Cache

— 4 Kbyte, Direct-Mapped Data Cache

— Sixteen 32-Bit Global Registers

— Sixteen 32-Bit Local Registers

— 1 Kbyte, Internal Data RAM

— Local Register Cache

(Eight Available Stack Frames)

— Two 32-Bit On-Chip Timer Units

PCI-to-PCI Bridge Unit

— Eight Delayed Read/Write Buffers

Holding up to eight Transactions

— Primary and Secondary 64-bit PCI

Interfaces

— Two Posting Buffers Holding up to 12

Transactions

— Delayed and Posted Transaction Support

— Forwards Memory, I/O, Configuration

Commands from PCI Bus to PCI Bus

O Messaging Unit

— Four Message Registers

— Two Doorbell Registers

— Four Circular Queues

— 1004 Index Registers

Memory Controller

— 128 Mbytes of 64-Bit SDRAM or

64 Mbytes of 32-Bit SDRAM

— ECC Single-Bit error correction,

Double-Bit error detection

— Two Independent Banks for SRAM /

ROM / Flash (8 Mbyte/Bank; 8-Bit)

Two Address Translation Units

— Connects Internal Bus to 64-bit PCI Buses

— Inbound/Outbound Address Translation

Support

— Direct Outbound Addressing Support

DMA Controller

— Three Independent Channels

— PCI Memory Controller Interface

— 64-Bit Internal + PCI Bus Addressing

— Independent Interface to 64-bit Primary

and Secondary PCI Buses

— 264 Mbyte/sec Burst Transfers to PCI and

SDRAM Memory

— Direct Addressing to/from PCI Buses

— Unaligned Transfers Supported in

Hardware

— Two Channels Dedicated to Primary PCI Bus

—One Channel Dedicated to Secondary PCI Bus

C Bus Interface Unit

— Serial Bus

— Master/Slave Capabilities

— System Management Functions

Secondary PCI Arbitration Unit

— Supports Six Secondary PCI Devices

— Multi-priority Arbitration Algorithm

Private PCI Device Support

Perimeter Land Grid Array Package

— 540-pin

Application Accelerator

— Built-in hardware XOR engine

Performance Monitoring

— Ninety-eight events monitored on-chip

Order Number: 273157-010

June, 2002

Intel

80960RN I/O Processor

Contents

1.0

About this Document

................................................................................................ 7

1.1

1.2

1.3

Intel

Solutions960

Program ............................................................................... 7

Terminology........................................................................................................... 7

Additional Information Sources ............................................................................. 7

2.0

Functional Overview

................................................................................................. 8

2.1

Key Functional Units ............................................................................................. 9

2.1.1 PCI-to-PCI Bridge Unit ............................................................................. 9

2.1.2 Private PCI Device Support...................................................................... 9

2.1.3 DMA Controller......................................................................................... 9

2.1.4 Address Translation Unit .......................................................................... 9

2.1.5 Messaging Unit......................................................................................... 9

2.1.6 Memory Controller Unit .......................................................................... 10

2.1.7 I2C Bus Interface Unit ............................................................................ 10

2.1.8 Secondary PCI Arbitration Unit .............................................................. 10

2.1.9 Application Accelerator Unit ................................................................... 10

2.1.10 Performance Monitor Unit ...................................................................... 10

2.1.11 Bus Interface Unit ................................................................................... 10

Intel

i960

Core Features (Intel

80960JT)....................................................... 11

2.2.1 Burst Bus................................................................................................ 12

2.2.2 Timer Unit ............................................................................................... 12

2.2.3 Priority Interrupt Controller ..................................................................... 12

2.2.4 Faults and Debugging ............................................................................ 12

2.2.5 On-Chip Cache and Data RAM .............................................................. 12

2.2.6 Local Register Cache ............................................................................. 13

2.2.7 Test Features ......................................................................................... 13

2.2.8 Memory-Mapped Control Registers ....................................................... 13

2.2.9 Instructions, Data Types and Memory Addressing Modes .....................13

2.2

3.0

Package Information

............................................................................................... 15

3.1

Package Introduction........................................................................................... 15

3.1.1 Functional Signal Definitions ..................................................................15

3.1.1.1 Signal Pin Descriptions ............................................................. 16

3.1.2 540-Lead H-PBGA Package ..................................................................26

Package Thermal Specifications .........................................................................38

3.2.1 Thermal Specifications ........................................................................... 38

3.2.1.1 Ambient Temperature................................................................ 38

3.2.1.2 Case Temperature .................................................................... 38

3.2.1.3 Thermal Resistance ..................................................................39

3.2.2 Thermal Analysis .................................................................................... 39

Heat Sink Information ..........................................................................................40

Vendor Information.............................................................................................. 40

3.4.1 Socket-Header Vendor........................................................................... 40

3.4.2 Burn-in Socket Vendor ........................................................................... 40

3.4.3 Shipping Tray Vendor............................................................................. 41

3.4.4 Logic Analyzer Interposer Vendor .......................................................... 41

3.4.5 JTAG Emulator Vendor .......................................................................... 41

............................................................................................................................ 41

3.2

3.3

3.4

3.5

Data Sheet

Intel

80960RN I/O Processor

Figures

Intel

80960RN Functional Block Diagram ..................................................... 8

Intel

80960JT Core Block Diagram ............................................................. 11

540L H-PBGA Package Diagram (Top and Side View) ................................ 26

540L H-PBGA Package Diagram (Bottom View) .......................................... 27

Thermocouple Attachment - A) No Heatsink / B) With Heatsink ................... 38

CC5REF

Current-Limiting Resistor................................................................ 43

CCPLL

Lowpass Filter .................................................................................. 43

P_CLK, TCK, DCLKIN, DCLKOUT Waveform.............................................

Output Delay Waveform......................................................................... 51

Output Float Waveform .......................................................................... 52

and T

Input Setup and Hold Waveform ................................................ 52

C Interface Signal Timings.......................................................................... 52

AC Test Load (all signals except SDRAM and Flash signals)....................... 53

Tables

Related Documentation................................................................................... 7

Instruction Set .............................................................................................. 14

Pin Description Nomenclature....................................................................... 16

Memory Controller Signals ............................................................................ 17

Primary PCI Bus Signals ............................................................................... 20

Secondary PCI Arbiter Signals...................................................................... 21

Secondary PCI Bus Signals .......................................................................... 22

Intel

80960Jx Core Signals and Configuration Straps................................. 24

C, JTAG, Core Signals ............................................................................... 25

540-Lead H-PBGA Package — Signal Name Order ..................................... 28

540-Lead H-PBGA Pinout — Ballpad Number Order.................................... 33

540-Lead H-PBGA Package Thermal Characteristics .................................. 39

Heat Sink Vendors and Contacts .................................................................. 40

Socket-Header Vendor.................................................................................. 40

Burn-in Socket Vendor .................................................................................. 40

Shipping Tray Vendor.................................................................................... 41

Logic Analyzer Interposer Vendor ................................................................. 41

JTAG Emulator Vendor ................................................................................. 41

Operating Conditions..................................................................................... 42

DIFF

Specification for Dual Power Supply Requirements (3.3 V, 5 V) ......... 43

DC Characteristics ........................................................................................ 44

Characteristics ........................................................................................ 45

Input Clock Timings....................................................................................... 46

SDRAM Output Clock Timings ...................................................................... 46

PCI Signal Timings....................................................................................... 47

Intel

80960JN Core Signal Timings............................................................. 48

SDRAM / Flash Signal Timings ..................................................................... 48

Boundary Scan Test Signal Timings ............................................................. 49

I2C Interface Signal Timings ......................................................................... 50

Device ID Registers...................................................................................... 54

Data Sheet

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