1. Input frequency range: 16 MHz to 33 MHz (FB_SEL = 1), or 25 MHz to 50 MHz (FB_SEL = 0).
Cypress Semiconductor Corporation
Document #: 38-07087 Rev. *C
•
3901 North First Street
•
San Jose
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CA 95134
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408-943-2600
Revised May 03, 2004
Z9960
Pin Definition
Pin Name
PECL_CLK
PECL_CLK#
TCLK
QA(6:0)
QB(6:0)
QC(6:0)
FB_OUT
No.
3
4
2
38, 39, 40, 42,
43, 45, 46
26, 27, 28, 30,
31, 33, 34
15, 16, 18, 19,
21, 22, 23
35
Type
I, PD
I, PU
I, PD
V
DDA
O
V
DDB
V
DDC
O
V
DD
I, PU
I, PU
I, PU
I, PU
I, PD
I, PU
I, PD
O
O
PECL Clock Input.
PECL Clock Input.
External Reference/Test Clock Input.
Clock Outputs.
See
Table 1
for frequency selections.
Clock Outputs.
See
Table 1
for frequency selections.
Clock Outputs.
See
Table 1
for frequency selections.
Feedback Clock Output.
Connect to FB_IN for normal operation. The divider
ratio for this output is set by FB_SEL; see
Table 1.
A bypass delay capacitor at
this output will control Input Reference/ Output Banks phase relationships.
Frequency Select Inputs.
These inputs select the divider ratio at QA(0:6)
outputs. See
Table 1.
Frequency Select Inputs.
These inputs select the divider ratio at QB(0:6)
outputs. See
Table 1.
Frequency Select Inputs.
These inputs select the divider ratio at QC(0:6)
outputs. See
Table 1.
Feedback Select Inputs.
These inputs select the divide ratio at FB_OUT output.
See
Table 1.
Feedback Clock Input.
Connect to FB_OUT for accessing the PLL.
Reference Select Input.
When high, the PECL clock is selected. And when low,
TCLK is the reference clock.
Output Enable Input.
When asserted low, enables all of the outputs. When
pulled high, disables to high impedance all of the outputs except FB_OUT.
Power Supply for Bank A Clock Buffers.
Power Supply for Bank B Clock Buffers.
Power Supply for Bank C Clock Buffers.
Power Supply for Core
Power Supply for PLL.
When AVDD is set low, PLL is bypassed.
Common Ground for Bank A.
Common Ground for Bank B.
Common Ground for Bank C.
Common Ground.
Pin Description
SELA
SELB
SELC
FB_SEL
FB_IN
REF_SEL
OE#
V
DDA
V
DDB
V
DDC
V
DD
AV
DD
V
SSA
V
SSB
V
SSC
V
SS
9
10
11
7
47
6
14
37, 44
25, 32
13, 20
5
8
36, 41
24, 29
12, 17
1, 48
A bypass capacitor (0.1µF) should be placed as close as possible to each positive power pin (< 0.2”). If these bypass capacitors
are not close to the pins, their high-frequency filtering characteristic will be cancelled by the lead inductance of the traces.
Document #: 38-07087 Rev. *C
Page 2 of 7
Z9960
Function Table
Control Pin
REF_SEL
AVDD
OE#
SELA
SELB
SELC
FB_SEL
TCLK
PLL Bypass, Outputs Controlled by OE#
Outputs Enabled
Output Bank A at VCO/2
Output Bank B at VCO/2
Output Bank C at VCO/2
Feedback Output at VCO/8
0
PECL_CLK
PLL Power
Outputs Disabled (except FB_OUT)
Output Bank A at VCO/4
Output Bank B at VCO/4
Output Bank C at VCO/4
Feedback Output at VCO/12
1
Overview
The Z9960 has an integrated PLL that provides low skew and
low jitter clock outputs for high-performance microprocessors.
Three independent banks of seven outputs as well as an
independent PLL feedback output, FB_OUT, provide excep-
tional flexibility for possible output configurations. The PLL is
ensured stable operation given that the VCO is configured to
run between 200 MHz to 400 MHz. This allows a wide range
of output frequencies up to 200 MHz.
The phase detector compares the input reference clock to the
external feedback input. For normal operation, the external
feedback input, FB_IN, is connected to the feedback output,
FB_OUT. The internal VCO is running at multiples of the input
reference clock set by FB_SEL select inputs; refer to
Table 1.
The VCO frequency is then divided down to provide the
required output frequencies.
Zero Delay Buffer
When used as a zero delay buffer the Z9960 will likely be in a
nested clock tree application. For these applications the
Z9960 offers a low-voltage PECL clock input as a PLL
reference. This allows the user to use LVPECL as the primary
clock distribution device to take advantage of its far-superior
skew performance. The Z9960 then can lock onto the LVPECL
reference and translate with near zero delay to low skew
outputs.
By using one of the outputs as a feedback to the PLL, the
propagation delay through the device is eliminated. The PLL
works to align the output edge, with the input reference edge
thus producing a near-zero delay. The reference frequency
affects the static phase offset of the PLL and thus the relative
delay between the inputs and outputs. Because the static
phase offset is a function of the reference clock, the Tpd of the
Z9960 is a function of the configuration used.
Document #: 38-07087 Rev. *C
Page 3 of 7
Z9960
Absolute Maximum Ratings
[2]
Input Voltage Relative to V
SS
:...............................V
SS
– 0.3V
Input Voltage Relative to V
DD
: ............................. V
DD
+ 0.3V
Storage Temperature: .................................-65°C to + 150°C
Operating Temperature: ................................-40°C to + 85°C
Maximum ESD Protection................................................ 2kV
Maximum Power Supply: ................................................5.5V
Maximum Input Current:..................................................± 20mA
Note:
2. The voltage on any input or I/O or pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric fields; however,
precautions should be taken to avoid application of any
voltage higher than the maximum rated voltages to this circuit.
For proper operation, V
IN
and V
OUT
should be constrained to
the range
V
SS
< (V
IN
or V
OUT
) < V
DD
.
Unused inputs must always be tied to an appropriate logic
voltage level (either V
SS
or V
DD
).
DC Electrical Characteristics
V
DD
= 2.5V ±5%, T
A
= –40°C to +85°C
Parameter
V
IL
[3]
[3]
Description
Input Low Voltage
Input High Voltage
Peak-to-Peak Input Voltage
PECL_CLK
Common Mode Range
PECL_CLK
Input Low Current (@ V
IL
= V
SS
)
Input High Current (@ V
IH
=
V
DD
)
Output Low Voltage
Output High Voltage
Quiescent Supply Current
Input Pin Capacitance
Test Condition
Min.
V
SS
1.7
500
V
DD
–1.4
–
–
Typ.
–
–
–
–
–
–
–
–
10
4
Max.
0.7
V
DD
1000
V
DD
–0.6
–120
120
0.6
13
–
Unit
V
V
mV
V
µA
µA
V
V
mA
pF
V
IH
V
PP
VCMR
[4]
I
IL[5]
I
IH[5]
V
OL[6]
V
OH[6]
I
DD
C
IN
I
OL
= 15 mA
I
OH
= –15 mA
V
DD
and AV
DD
–
1.8
–
–
DC Electrical Characteristics
V
DD
= 3.3V +5%, T
A
= –40°C to +85°C
Parameter
V
IL[3]
V
IH[3]
V
PP
VCMR
[4]
I
IL[5]
I
IH[5]
V
OL[6]
V
OH
[6]
Description
Input Low Voltage
Input High Voltage
Peak-to-Peak Input Voltage
PECL_CLK
Common Mode Range PECL_CLK
Input Low Current (@ V
IL
= V
SS
)
Input High Current (@ V
IH
= V
DD
)
Output Low Voltage
Output High Voltage
Quiescent Supply Current
Input Pin Capacitance
Test Condition
Min.
V
SS
2.0
500
V
DD
–1.4
–
–
Typ.
–
–
–
–
–
–
–
–
15
4
Max.
0.8
V
DD
1000
V
DD
–0.6
–120
120
0.55
–
20
–
Unit
V
V
mV
V
µA
µA
V
V
mA
pF
I
OL
= 24 mA
I
OH
= –24 mA
V
DD
and AV
DD
–
2.4
–
–
I
DD
C
IN
Notes:
3. The LVCMOS inputs threshold is at 30% of V
DD
.
4. The VCMR is the difference from the most positive side of the differential input signal. Normal operation is obtained when HIGH input is within the VCMR range
and the input lies within the V
PP
specification.
5. Inputs have pull-up/pull-down resistors that affect input current.
6. Driving series or parallel terminated 50Ω (or 50Ω to V
DD
/2) transmission lines.
Document #: 38-07087 Rev. *C
Page 4 of 7
Z9960
AC Electrical Characteristics
V
DD
= 2.5V ±5% or 3.3V ±5%, T
A
= –40°C to +85°C
[7]
Symbol
Fref
FrefDC
Fvco
Tlock
Tr / Tf
Fout
FoutDC
tpZL, tpZH
tpLZ, tpHZ
TCCJ
Tskew
Tskew
Tskew(pp)
Tpd
Parameter
Reference Input Frequency
Reference Input Duty Cycle
PLL VCO Lock Range
Maximum PLL lock Time
Output Clocks Rise / Fall
Time
[8],[9]
Maximum Output Frequency
Output Duty
Cycle
[8],[9]
0.55V to 2.0V, V
DD
= 3.3V
0.5V to 1.8V, V
DD
= 2.5V
Q (÷2)
Q (÷4)
Output Enable Time
[8]
(all
outputs)
Output Disable Time
[8]
(all
outputs)
Cycle to Cycle Jitter
[8],[9]
Any Output to Any Output
Skew
[8],[9]
Bank to Bank Skew
Part to Part
Phase
Error
[8],[9]
Skew
[10]
TCLK or
PECL_CLK to
FB_IN
V
DD
= 3.3V
V
DD
= 2.5V
Same frequency
Different frequency
Banks at different voltages
Test Condition
FB_SEL = 1
FB_SEL = 0
Min.
16
25
25
200
–
0.1
–
100
50
45
2
2
–
–
–
–
–
0
25
Typ.
–
–
–
–
–
–
–
–
–
50
–
–
±100
–
–
–
–
100
125
Max.
33
50
75
400
10
1.0
–
200
100
55
10
8
–
150
300
400
450
200
225
ps
ps
ps
%
ns
ns
ps
ps
MHz
%
MHz
ms
ns
Unit
MHz
Note:
7. Parameters are guaranteed by design and characterization. Not 100% tested in production.
8. Outputs loaded with 30pF each.
9. 50Ω transmission line terminated into VDD/2.
10. Part to Part skew at a given temperature and voltage
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Microcontroller MCU
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