Am29F160D
Data Sheet
Am29F160D Cover Sheet
The following document contains information on Spansion memory products.
Continuity of Specifications
There is no change to this data sheet as a result of offering the device as a Spansion product. Any changes that have been
made are the result of normal data sheet improvement and are noted in the document revision summary.
For More Information
Please contact your local sales office for additional information about Spansion memory solutions.
Publication Number
Am29F160D_00
Revision
D
Amendment
10
Issue Date
April 23, 2010
D at a
S hee t
This page left intentionally blank.
2
Am29F160D
Am29F160D_00_D10 April 23, 2010
DATA SHEET
Am29F160D
16 Megabit (2 M x 8-Bit/1 M x 16-Bit)
CMOS 5.0 Volt-only, Boot Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
■
5.0 Volt single power supply operation
— Minimizes system-level power requirements
■
High performance
— Access times as fast as 70 ns
■
Manufactured on 0.23 µm process technology
■
CFI (Common Flash Interface) compliant
— Provides device-specific information to the
system, allowing host software to easily
reconfigure for different Flash devices
■
Ultra low power consumption (typical values at
5 MHz)
— 15 mA typical active read current
— 35 mA typical erase/program current
— 300 nA typical standby mode current
■
Flexible sector architecture
— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and
thirty-one 64 Kbyte sectors (byte mode)
— One 8 Kword, two 4 Kword, one 16 Kword, and
thirty-one 32 Kword sectors (word mode)
— Supports full chip erase
— Sector Protection features:
— Hardware method of locking a sector to prevent
program or erase operations within that sector
— Sectors can be locked in-system or via
programming equipment
— Temporary Sector Unprotect feature allows code
changes in previously locked sectors
■
Top boot or bottom boot configurations
available
■
Minimum 1,000,000 write cycle guarantee
per sector
■
20-year data retention at 125° C
— Reliable operation for the life of the system
■
Package options
— 48-pin TSOP
■
Compatible with JEDEC standards
— Pinout and software compatible with single-
power supply Flash
— Superior inadvertent write protection
■
Embedded Algorithms
— Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
— Embedded Program algorithm automatically
writes and verifies data at specified addresses
■
Erase Suspend/Erase Resume
— Suspends an erase operation to read data from,
or program data to, a sector that is not being
erased, then resumes the erase operation
■
Data# Polling and toggle bits
— Provides a software method of detecting
program or erase operation completion
■
Unlock Bypass Program command
— Reduces overall programming time when
issuing multiple program command sequences
■
Ready/Busy# pin (RY/BY#)
— Provides a hardware method of detecting
program or erase cycle completion
■
Hardware reset pin (RESET#)
— Hardware method to reset the device for reading
array data
■
WP# input pin
— At
VIL
, protects the 16 Kbyte boot sector from
erasure regardless of sector protect/unprotect
status
— At V
IH
, allows removal of boot sector protection
■
Program and Erase Performance
— Sector erase time: 1 s typical for each 64 Kbyte
sector
— Byte program time: 7 µs typical
This Data Sheet states AMD’s current technical specifications regarding the Product described herein. This Data
Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
Publication#
Am29F160D_00
Revision:
D
Amendment:
10
Issue Date:
April 23, 2010
DATA SHEET
GENERAL DESCRIPTION
The Am29F160D is a 16 Mbit, 5.0 Volt-only Flash
memory device organized as 2,097,152 bytes or
1,048,576 words. Data appears on DQ0-DQ7 or DQ0-
DQ15 depending on the data width selected. The
device is designed to be programmed in-system with
the standard system 5.0 volt V
CC
supply. A 12.0 volt
V
PP
is not required for program or erase operations.
The device can also be programmed in standard
EPROM programmers.
The device offers access times of 70 and 90 ns, allowing
high speed microprocessors to operate without wait
states. The device is offered in a 48-pin TSOP
package. To eliminate bus contention each device has
separate chip enable (CE#), write enable (WE#) and
output enable (OE#) controls.
Each device requires only a
single 5.0 volt power
supply
for both read and write functions. Internally
generated and regulated voltages are provided for the
program and erase operations.
The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard.
Com-
mands are written to the command register using stan-
dard microprocessor write timing. Register contents
serve as inputs to an internal state-machine that con-
trols the erase and programming circuitry. Write cycles
also internally latch addresses and data needed for the
programming and erase operations. Reading data out
of the device is similar to reading from other Flash or
EPROM devices.
Device programming occurs by executing the program
command sequence. This initiates the
Embedded
Program
algorithm—an internal algorithm that auto-
matically times the program pulse widths and verifies
proper cell margin. The
Unlock Bypass mode
facili-
tates faster programming times by requiring only two
write cycles to program data instead of four.
Device erasure occurs by executing the erase
command sequence. This initiates the
Embedded
Erase algorithm—an
internal algorithm that automati-
cally preprograms the array (if it is not already pro-
grammed) before executing the erase operation.
During erase, the device automatically times the erase
pulse widths and verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, by reading the DQ7 (Data# Polling), or DQ6
(toggle)
status bits.
After a program or erase cycle is
completed, the device is ready to read array data or
accept another command.
The
sector erase architecture
allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection
measures include a low
VCC detector that automatically inhibits write operations
during power transitions. The
hardware sector protec-
tion
feature disables both program and erase operations
in any combination of sectors of memory. This can be
achieved in-system or via programming equipment.
The
Write Protect (WP#)
feature protects the 16
Kbyte boot sector from erasure, by asserting a logic
low on the WP# pin, whether or not the sector had
been previously protected.
The
Erase Suspend/Erase Resume
feature enables
the user to put erase on hold for any period of time to
read data from, or program data to, any sector that is
not selected for erasure. True background erase can
thus be achieved.
The
hardware RESET# pin
terminates any operation
in progress and resets the internal state machine to
reading array data. The RESET# pin may be tied to the
system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor
to read boot-up firmware from the Flash memory device.
The device offers a
standby mode
as a power-saving
feature. Once the system places the device into the
standby mode power consumption is greatly reduced.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective-
ness. The device electrically erases all bits within a
sector simultaneously via Fowler-Nordheim tunnelling.
The data is programmed using hot electron injection.
2
Am29F160D
Am29F160D_00_D10 April 23, 2010
DATA SHEET
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 5
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 7
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 8
Table 1. Am29F160D Device Bus Operations . . . . . 8
Word/Byte Configuration . . . . . . . . . . . . . . . . . . . . . 8
Requirements for Reading Array Data . . . . . . . . . . . 8
Writing Commands/Command Sequences . . . . . . . 9
Program and Erase Operation Status . . . . . . . . . . . 9
Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Automatic Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . 9
RESET#: Hardware Reset Pin . . . . . . . . . . . . . . . . . 9
Output Disable Mode . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 2. Am29F160DT Sector Address Table (Top
Boot) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 3. Am29F160DB Sector Address Table (Bottom
Boot) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Autoselect Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 4. Am29F160D Autoselect Codes (High Voltage
Method) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Sector Protection/Unprotection . . . . . . . . . . . . . . . 12
Write Protect (WP#) . . . . . . . . . . . . . . . . . . . . . . . . 13
Temporary Sector Unprotect . . . . . . . . . . . . . . . . . 13
Figure 1. Temporary Sector Unprotect Operation . 13
In-System Sector Protect/Unprotect Algorithms. . . 14
Common Flash Memory Interface (CFI) . . . . . . . 15
Table 5. CFI Query Identification String . . . . . . . . . 15
Table 6. System Interface String . . . . . . . . . . . . . . 16
Table 7. Device Geometry Definition . . . . . . . . . . . 16
Table 8. Primary Vendor-Specific Extended Query 17
Hardware Data Protection . . . . . . . . . . . . . . . . . . . 18
Reading Array Data . . . . . . . . . . . . . . . . . . . . . . . . 18
Reset Command . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Autoselect Command Sequence . . . . . . . . . . . . . . 19
Word/Byte Program Command Sequence. . . . . . . 19
Figure 3. Program Operation . . . . . . . . . . . . . . . . . 20
Chip Erase Command Sequence . . . . . . . . . . . . . 20
Sector Erase Command Sequence . . . . . . . . . . . . 20
Erase Suspend/Erase Resume Commands . . . . . 21
Figure 4. Erase Operation . . . . . . . . . . . . . . . . . . . 21
Command Definitions. . . . . . . . . . . . . . . . . . . . . . . 22
Table 9. Am29F160D Command Definitions . . . . . 22
Write Operation Status . . . . . . . . . . . . . . . . . . . . 23
DQ7: Data# Polling . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 5. Data# Polling Algorithm . . . . . . . . . . . . . . 23
RY/BY#: Ready/Busy# . . . . . . . . . . . . . . . . . . . . . . 24
DQ6: Toggle Bit I . . . . . . . . . . . . . . . . . . . . . . . . . . 24
DQ2: Toggle Bit II . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Reading Toggle Bits DQ6/DQ2. . . . . . . . . . . . . . . . 24
DQ5: Exceeded Timing Limits . . . . . . . . . . . . . . . . 25
DQ3: Sector Erase Timer . . . . . . . . . . . . . . . . . . . . 25
Figure 6. Toggle Bit Algorithm . . . . . . . . . . . . . . . . 25
Table 10. Write Operation Status . . . . . . . . . . . . . . 26
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . 27
Figure 7. Maximum Negative Overshoot Waveform 27
Figure 8. Maximum Positive Overshoot Waveform. 27
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 27
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 28
TTL/NMOS Compatible. . . . . . . . . . . . . . . . . . . . . . 28
CMOS Compatible . . . . . . . . . . . . . . . . . . . . . . . . . 29
Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 9. Test Setup . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 11. Test Specifications . . . . . . . . . . . . . . . . . 30
Key to Switching Waveforms. . . . . . . . . . . . . . . . 30
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 10. Read Operations Timings . . . . . . . . . . . 31
Figure 11. RESET# Timings . . . . . . . . . . . . . . . . . . 32
Figure 12. BYTE# Timings for Read Operations . . 33
Figure 13. BYTE# Timings for Write Operations. . . 33
Figure 14. Program Operation Timings. . . . . . . . . . 35
Figure 15. Chip/Sector Erase Operation Timings . . 36
Figure 16. Data# Polling Timings (During Embedded
Algorithms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 17. Toggle Bit Timings (During Embedded Algo-
rithms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 18. DQ2 vs. DQ6 . . . . . . . . . . . . . . . . . . . . . 38
Figure 19. Temporary Sector Unprotect Timing Dia-
gram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 20. Sector Protect/Unprotect
Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 21. Alternate CE# Controlled Write Operation
Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Erase and Programming Performance . . . . . . . . 42
Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 42
TSOP and SO Pin Capacitance . . . . . . . . . . . . . . 42
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 43
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 44
April 23, 2010 Am29F160D_00_D10
Am29F160D
3
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