HIGH-SPEED 3.3V 16/8K X 9
SYNCHRONOUS PIPELINED
DUAL-PORT STATIC RAM
Features:
◆
◆
◆
IDT70V9169/59L
◆
◆
◆
◆
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed clock to data access
– Commercial: 6.5/7.5/9ns (max.)
– Industrial: 7.5ns (max.)
Low-power operation
– IDT70V916/59L/59L
Active: 450mW (typ.)
Standby: 1.5mW (typ.)
Flow-Through or Pipelined output mode on either port via
the
FT/PIPE
pins
Counter enable and reset features
Dual chip enables allow for depth expansion without
additional logic
◆
◆
◆
◆
Full synchronous operation on both ports
– 3.5ns setup to clock and 0ns hold on all control, data, and
address inputs
– Data input, address, and control registers
– Fast 6.5ns clock to data out in the Pipelined output mode
– Self-timed write allows fast cycle time
– 10ns cycle time, 100MHz operation in Pipelined output mode
Separate upper-byte and lower-byte controls for
multiplexed bus and bus matching compatibility
LVTTL- compatible, single 3.3V (±0.3V) power supply
Industrial temperature range (–40°C to +85°C) is
available for 83 MHz
Available in a 100-pin Thin Quad Flatpack (TQFP) and 100-
pin fine pitch Ball Grid Array (fpBGA) packages.
Functional Block Diagram
R/W
L
OE
L
CE
0L
CE
1L
R/W
R
OE
R
CE
0R
CE
1R
1
0
0/1
1
0
0/1
FT/PIPE
L
0/1
1
0
0
1
0/1
FT/PIPE
R
I/O
0L
- I/O
8L
I/O
0R
- I/O
8R
I/O
Control
I/O
Control
A
13L
(1)
A
0L
CLK
L
ADS
L
CNTEN
L
CNTRST
L
NOTE:
1. A
13
is a NC for IDT70V9159.
A
13R
(1)
Counter/
Address
Reg.
MEMORY
ARRAY
Counter/
Address
Reg.
A
0R
CLK
R
ADS
R
CNTEN
R
CNTRST
R
5655 drw 01
AUGUST 2003
1
©2003 Integrated Device Technology, Inc.
DSC-5655/2
N T:
OE
.
A
13
sa
NC
or
TV5
799
01
IDT70V9169/59L
High-Speed 3.3V 16/8K x 9 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
The IDT70V9169/59 is a high-speed 16/8K x 9 bit synchronous
Dual-Port RAM. The memory array utilizes Dual-Port memory cells
to allow simultaneous access of any address from both ports.
Registers on control, data, and address inputs provide minimal setup
and hold times. The timing latitude provided by this approach allows
systems to be designed with very short cycle times.
Description:
With an input data register, the IDT70V9169/59 has been optimized
for applications having unidirectional or bidirectional data flow in bursts. An
automatic power down feature, controlled by
CE
0
and CE
1,
permits the
on-chip circuitry of each port to enter a very low standby power mode.
Fabricated using IDT’s CMOS high-performance technology, these
devices typically operate on only 450mW of power.
Pin Configurations
(1,2,3,4)
06/21/02
Index
NC
NC
A
7L
A
8L
A
9L
A
10L
A
11L
A
12L
A
13L
(1)
NC
NC
NC
V
DD
NC
NC
NC
NC
CE
0L
CE
1L
CNTRST
L
R/W
L
OE
L
FT/PIPE
L
NC
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
75
2
74
3
73
1
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
72
71
70
69
68
NC
NC
A
6L
A
5L
A
4L
A
3L
A
2L
A
1L
A
0L
CNTEN
L
CLK
L
ADS
L
Vss
Vss
ADS
R
CLK
R
CNTEN
R
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
A
6R
NC
70V9169/59PF
PN100-1
(5)
100-Pin TQFP
Top View
(6)
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC
NC
A
7R
A
8R
A
9R
A
10R
A
11R
A
12R
A
13R
(1)
NC
NC
NC
Vss
NC
NC
NC
NC
CE
0R
CE
1R
CNTRST
R
R/W
R
OE
R
FT/PIPE
R
Vss
NC
5655 drw 02
NOTES:
1. A
13
is a NC for IDT70V9159.
2. All V
DD
pins must be connected to power supply.
3. All V
SS
pins must be connected to ground supply.
4. Package body is approximately 14mm x 14mm x 1.4mm.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
Vss
I/O
8L
I/O
7L
I/O
6L
I/O
5L
I/O
4L
I/O
3L
I/O
2L
Vss
I/O
1L
I/O
0L
V
DD
Vss
I/O
0R
I/O
1R
I/O
2R
V
DD
I/O
3R
I/O
4R
I/O
5R
I/O
6R
I/O
7R
I/O
8R
NC
NC
.
6.42
2
IDT70V9169/59L
High-Speed 3.3V 16/8K x 9 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Pin Configurations(cont'd)
(1,2,3,4)
70V9169/59PF
BF100
(5)
100-Pin fpBGA
Top View
(6)
06/21/02
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A
6R
B1
A
9R
B2
A
12R
B3
NC
B4
V
SS
B5
V
SS
B6
NC
B7
R/W
R
B8
V
SS
B9
NC
B10
A
4R
C1
A
5R
C2
A
8R
C3
A
10R
C4
NC
C5
NC
C6
NC
C7
OE
R
C8
NC
C9
I/O
6R
C10
A
3R
D1
NC
D2
NC
D3
A
7R
D4
NC
D5
CE
0R
CE
1R
PL/FT
R
I/O
7R
I/O
3R
D6
D7
CNTRST
R
D8
D9
D10
A
0R
E1
CLK
R
E2
A
1R
E3
CNTEN
R
F3
A
2R
E4
A
11R
E5
A
13R
(1)
E6
I/O
8R
E8
I/O
5R
I/O
1R
E9
E10
E7
V
SS
F1
ADS
R
F2
A
1L
F4
ADS
L
F5
V
SS
F6
I/O
4R
F7
I/O
2R
F8
I/O
0R
F9
V
DD
F10
V
SS
G1
CNTEN
L
H1
CLK
L
G2
A
0L
G3
A
3L
G4
V
DD
G5
V
SS
G6
V
DD
G7
I/O
2L
G8
I/O
1L
G9
I/O
0L
G10
NC
H2
A
5L
H3
A
12L
H4
H5
NC
R/W
L
H6
NC
H7
I/O
4L
H8
V
SS
H9
I/O
3L
H10
,
A
2L
J1
A
4L
J2
A
9L
J3
A
13L
(1)
J4
NC
J5
CE
1L
J6
NC
J7
I/O
7L
J8
I/O
6L
J9
I/O
5L
J10
NC
K1
A
7L
K2
A
10L
K3
NC
K4
NC
K5
NC
K6
OE
L
K7
V
SS
K8
CNTRST
L
V
SS
K9
I/O
8L
K10
A
6L
A
8L
A
11L
NC
V
DD
V
DD
CE
0L
PL/FT
L
NC
5655 drw 03
NOTES:
1. A
13
is a NC for IDT70V9159.
2. All V
DD
pins must be connected to power supply.
3. All V
SS
pins must be connected to ground supply.
4. Package body is approximately 10mm x 10mm x 1.4mm with 0.8mm ball pitch.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
6.42
3
IDT70V9169/59L
High-Speed 3.3V 16/8K x 9 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Pin Names
Left Port
CE
0L
, CE
1L
R/W
L
OE
L
A
0L
- A
13L
(1)
I/O
0L
- I/O
8L
CLK
L
ADS
L
CNTEN
L
CNTRST
L
FT/PIPE
L
Right Port
CE
0R
, CE
1R
R/W
R
OE
R
A
0R
- A
13R
(1)
I/O
0R
- I/O
8R
CLK
R
ADS
R
CNTEN
R
CNTRST
R
FT/PIPE
R
V
DD
V
SS
NOTE:
1. A
13
is a NC for IDT70V9159.
Names
Chip Enables
Read/Write Enable
Output Enable
Address
Data Input/Output
Clock
Address Strobe
Counter Enable
Counter Reset
Flow-Through/Pipeline
Power (3.3V)
Ground (0V)
5655 tbl 01
Truth Table I—Read/Write and Enable Control
(1,2,3)
OE
X
X
X
L
H
CLK
↑
↑
↑
↑
X
CE
0
H
X
L
L
L
CE
1
X
L
H
H
H
R/W
X
X
L
H
X
I/O
0-8
High-Z
High-Z
DATA
IN
DATA
OUT
High-Z
Mode
Deselected—Power Down
Deselected—Power Down
Write
Read
Outputs Disabled
5655 tbl 02
NOTES:
1. "H" = V
IH,
"L" = V
IL,
"X" = Don't Care.
2.
ADS, CNTEN, CNTRST
= X.
3.
OE
is an asynchronous input signal.
6.42
4
IDT70V9169/59L
High-Speed 3.3V 16/8K x 9 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Truth Table II—Address Counter Control
(1,2)
External
Address
An
X
X
X
Previous
Internal
Address
X
An
An + 1
X
Internal
Address
Used
An
An + 1
An + 1
A
0
CLK
↑
↑
↑
↑
ADS
L
(4)
H
H
X
CNTEN
X
L
(5)
H
X
CNTRST
H
H
H
L
(4)
I/O
(3)
D
I/O
(n)
D
I/O
(n+1)
D
I/O
(n+1)
D
I/O
(0)
External Address Used
Counter Enabled—Internal Address generation
External Address Blocked—Counter disabled (An + 1 reused)
Counter Reset to Address 0
5655 tbl 03
MODE
NOTES:
1. "H" = V
IH,
"L" = V
IL,
"X" = Don't Care.
2.
CE
0
,
LB, UB,
and
OE
= V
IL
; CE
1
and R/W = V
IH
.
3. Outputs configured in Flow-Through Output mode: if outputs are in Pipelined mode the data out will be delayed by one cycle.
4.
ADS
and
CNTRST
are independent of all other signals including
CE
0
, CE
1
,
UB
and
LB.
5. The address counter advances if
CNTEN
= V
IL
on the rising edge of CLK, regardless of all other signals including
CE
0
, CE
1
,
UB
and
LB.
Recommended Operating
Temperature and Supply Voltage
Grade
Commercial
Industrial
Ambient
Temperature
(1)
0 C to +70 C
O
O
Recommended DC Operating
Conditions
Symbol
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Min.
3.0
0
2.0
-0.3
(1)
Typ.
3.3
0
____
____
Max.
3.6
0
V
DD
+0.3V
(2)
0.8
Unit
V
V
V
V
5655 tbl 05
GND
0V
0V
V
DD
3.3V
+
0.3V
3.3V
+
0.3V
5655 tbl 04
V
DD
V
SS
V
IH
V
IL
-40
O
C to +85
O
C
NOTES:
1. This is the parameter T
A
. This is the "instant on" case temperature.
NOTES:
1. V
IL
> -1.5V for pulse width less than 10 ns.
2. V
TERM
must not exceed V
DD
+0.3V.
Absolute Maximum Ratings
(1)
Symbol
V
TERM
(2)
Capacitance
(1)
Unit
V
Rating
Terminal Voltage
with Respect to
GND
Temperature
Under Bias
Storage
Temperature
DC Output Current
Commercial
& Industrial
-0.5 to +4.6
(T
A
= +25°C, f = 1.0MH
Z
)
Symbol
C
IN
C
OUT
(3)
Parameter
Input Capacitance
Output Capacitance
Conditions
(2)
V
IN
= 3dV
V
OUT
= 3dV
Max.
9
10
Unit
pF
pF
5655 tbl 07
T
BIAS
T
STG
I
OUT
-55 to +125
-65 to +150
50
o
C
C
o
mA
5655 tbl 06
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. V
TERM
must not exceed V
DD
+0.3V for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of V
TERM
> V
DD
+ 0.3V.
NOTES:
1. These parameters are determined by device characterization, but are not
production tested.
2. 3dV references the interpolated capacitance when the input and output switch
from 0V to 3V or from 3V to 0V.
3. C
OUT
also references C
I/O
.
6.42
5
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