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STRUCTURE
TYPE
PRODUCT SERIES
FUNCTION
Silicon Monolithic Integrated Circuit
Regulator IC for Memory Termination
BD3538FVM
・Built-in
Push-pull Amplifier for Termination (VTT)
・Built-in
Reference Voltage Circuit (VREF)
・Dual
Channel (DDR-Ⅱ)
○ABSOLUTE
MAXIMUM RATINGS（Ta=25℃）
Parameter
Input Voltage
Enable Input Voltage
Termination Input Voltage
VDDQ Reference Voltage
Output Current
Power Dissipation
Operating Temperature Range
Storage Temperature Range
Maximum Junction Temperature
Symbol
VCC
VEN
VTT_IN
VDDQ
ITT
Pd
Topr
Tstg
Tjmax
Limit
7
*1*2
7
*1*2
7
*1*2
7
*1*2
1
437.5
*3
-40½+105
-55½+150
+150
Unit
V
V
V
V
A
mW
℃
℃
℃
*1 Should not exceed Pd.
*2 Instantaneous surge voltage, back electromotive force and voltage under less than 10% duty cycle.
*3 Reduced by 3.5mW for each increase in Ta of 1℃ over 25℃（With no heat sink）.
○OPERATING
CONDITIONS（Ta=25℃）
Parameter
Input Voltage
Termination Input Voltage
VDDQ Reference Voltage
Enable Input Voltage
★
Symbol
VCC
VTT_IN
VDDQ
VEN
MIN
2.7
1.0
1.0
-0.3
MAX
5.5
5.5
2.75
5.5
Unit
V
V
V
V
This product is designed for protection against radioactive rays.
Status of this document
The Japanese version of this document is the official specification.
This translated version is intended only as a reference, to aid in understanding the official version.
If there are any differences between the original and translated versions of this document, the official Japanese language version takes priority.
REV. B
2/4
○ELECTRICAL
CHARACTERISTICS
(unless otherwise noted, Ta=25℃, VCC=3.3V, VEN=3V, VDDQ=1.8V, VTT_IN=1.8V）
Standard Value
Parameter
Symbol
Unit
Condition
MIN
TYP
MAX
Standby Current
IST
-
0.5
1.0
mA VEN=0V
Bias Current
ICC
-
2
4
mA VEN=3V
[Enable]
High Level Enable Input
VENHIGH
2.3
-
5.5
V
Voltage
Low Level Enable Input
VENLOW
-0.3
-
0.8
V
Voltage
Enable Pin Input Current
IEN
-
7
10
uA VEN=3V
[Termination]
ITT=-1.0A to 1.0A
Termination Output Voltage 1
VTT1
VREF-30m
VREF
VREF+30m
V
Ta=0℃ to 105℃
VCC=5V, VDDQ=2.5V
VTT_IN=2.5V
Termination Output Voltage 2
VTT2
VREF-30m
VREF
VREF+30m
V
ITT=-1.0A to 1.0A
Ta=0℃ to 105℃
Source Current
ITT+
1.0
-
-
A
Sink Current
ITT-
-
-
-1.0
A
⊿VTT
Load Regulation
-
-
50
mV ITT=-1.0A to 1.0A
Line Regulation
Reg.l
-
20
40
mV
Ω
Upper Side ON Resistance 1 HRON1
-
0.45
0.9
Ω
Lower Side ON Resistance 1 LRON1
-
0.45
0.9
Vcc=5V, VDDQ=2.5V
Ω
Upper Side ON Resistance 2 HRON2
-
0.4
0.8
VTT_IN=2.5V
Vcc=5V, VDDQ=2.5V
Ω
Lower Side ON Resistance 2 LRON2
-
0.4
0.8
VTT_IN=2.5V
[Input of Reference Voltage]
kΩ
Input Impedance
ZVDDQ
70
100
130
Output Voltage 1
Output Voltage 2
VREF1
VREF2
1/2×VDDQ
1/2×VDDQ
1/2×VDDQ
+18m
-18m
1/2×VDDQ
1/2×VDDQ
1/2×VDDQ
+40m
-40m
1/2×VDDQ
1/2×VDDQ
1/2×VDDQ
+25m
-25m
V
V
IREF=-5mA to 5mA
Ta=0℃ to 105℃
IREF=-10mA to 10mA
Ta=0℃ to 105℃
VCC=5V, VDDQ=2.5V
VTT_IN=2.5V
IREF=-5mA to 5mA
Ta=0℃ to 105℃
VCC=5V, VDDQ=2.5V
VTT_IN=2.5V
IREF=-10mA to 10mA
Ta=0℃ to 105℃
VCC : sweep up
VCC : sweep down
Output Voltage 3
VREF3
V
Output Voltage 4
[UVLO]
UVLO OFF Voltage
Hysteresis Voltage
VREF4
1/2×VDDQ
1/2×VDDQ
1/2×VDDQ
+40m
-40m
V
VUVLO
⊿VUVLO
2.40
100
2.55
160
2.70
220
V
mV
REV. B
3/4
○PHYSICAL
DIMENSION
D 3 5
3
8
1PIN MARK Lot No.
(UNIT:mm)
MSOP8
○BLOCK
DIAGRAM
VCC
C2
○Pin
number Pin name
VDDQ
VTT_IN
C3
VCC
6
VCC
VDDQ
5
VCC
VCC
VTT_IN
7
Reference
Block
-
+
SOFT
UVLO
UVLO
TSD
EN
UVLO
+
-
VCC
TSD
EN
UVLO
VTT
8
C4
-
+
VTT
Thermal
Protection
EN
2
TSD
TSD
EN
UVLO
3
VTTS
4
VREF
C1
Enable
EN
1
½×
VDDQ
Pin
number
1
2
3
4
5
6
7
8
Pin name
GND
EN
VTTS
VREF
VDDQ
VCC
VTT_IN
VTT
GND
REV. B
4/4
○NOTES
FOR USE
(1)
Absolute maximum range
Although the quality of this product is rigorously controlled, and circuit operation is guaranteed within the operation ambient
temperature range, the device may be destroyed when applied voltage or operating temperature exceeds its absolute maximum
rating. Because the failure mode (such as short mode or open mode) cannot be identified in this instance, it is important to take
physical safety measures such as fusing if a specific mode in excess of absolute rating limits is considered for implementation.
Ground potential
Make sure the potential for the GND pin is always kept lower than the potentials of all other pins, regardless of the operating
mode, including transient conditions.
Thermal Design
Provide sufficient margin in the thermal design to account for the allowable power dissipation (Pd) expected in actual use.
Using in the strong electromagnetic field
Use in strong electromagnetic fields may cause malfunctions.
ASO
Be sure that the output transistor for this IC does not exceed the absolute maximum ratings or ASO value.
Thermal shutdown circuit
The IC is provided with a built-in thermal shutdown (TSD) circuit. When chip temperature reaches the threshold temperature
shown below, output goes to a cut-off (open) state. Note that the TSD circuit is designed exclusively to shut down the IC in
abnormal thermal conditions. It is not intended to protect the IC per se or guarantee performance when extreme heat occurs.
Therefore, the TSD circuit should not be employed with the expectation of continued use or subsequent operation once TSD is
operated.
TSD ON temperature [℃]
175
(7)
(typ.)
Hysteresis temperature [℃]
15
(typ.)
(2)
(3)
(4)
(5)
(6)
GND pattern
When both a small-signal GND and high current GND are present, single-point grounding (at the set standard point) is
recommended, in order to separate the small-signal and high current patterns, and to be sure the voltage change stemming from
the wiring resistance and high current does not cause any voltage change in the small-signal GND. In the same way, care must
be taken to avoid wiring pattern fluctuations in any connected external component GND.
(8) Output Capacitor (C1)
Mount an output capacitor between VREF and GND for stability purposes. The VREF output capacitor is for the open loop gain
phase compensation. If the capacitor value is not large enough, the output voltage may oscillate. A ceramic 1.0 - 10uF capacitor
with minimal susceptibility to temperature is recommended. However, this stability depends on the characteristics of temperature
and load. Please confirm operation across a variety of temperature and load conditions.
(9) Output Capacitor (C4)
Mount an output capacitor between VTT and GND for stability purposes. The output capacitor is for the open loop gain phase
compensation and reduces the output voltage load regulation. If the capacitor value is not large enough, the output voltage may
oscillate. And if the equivalent series resistance (ESR) is too large, the output voltage rise/drop increases during a sudden load
change. A 47 - 220uF polymer capacitor is recommended. However, the stability depends on the characteristics of temperature
and load conditions. And if a small ESR capacitor such as a ceramic capacitor is utilized, the output voltage may oscillate due to
lack of phase margin. In this case, measures can be taken by adding a resistor in series with this capacitor. Please confirm
operation across a variety of temperature and load conditions.
(10) Input Capacitor (C2, C3)
The input capacitor reduces the output impedence of the voltage supply source connected in the VCC and VTT_IN. If the output
impedence of this power supply increases, the input voltage (VCC,VTT_IN) may become unstable. This may result in the output
voltage oscillation or lowering ripple rejection. A low ESR 1uF capacitor in VCC and 10uF capacitor in VTT_IN with minimal
susceptibility to temperature are preferable, but stability depends on power supply characteristics and the substrate wiring
pattern (a parasitic capacitance and impedance). Please confirm operation across a variety of temperature and load conditions.
(11) Input
（VCC,
VDDQ, VTT_IN, EN）
The VCC, VDDQ, VTT_IN, and EN are isolated. The UVLO function is integrated to protect faulty operation due to low voltage
levels of VCC. VTT output voltage starts up when VCC reaches the UVLO threshold level and EN reaches the threshold level
respectively regardless of the start up order in those inputs. And also VREF output voltage starts up when VCC reaches the
UVLO threshold level. When the VDDQ and VTT_IN has the same voltage and are supposed to connect each other, VDDQ pin
voltage may change due to the voltage drop on the VTT_IN and VDDQ common wiring caused by VTT_IN input current change.
This may result in the voltage change of the VTT output. Avoid drawing wiring pattern of VDDQ and VTT_IN so that they do not
have common wiring. If the common wiring is inevitable due to limited PCB area, it is recommended that CR filter be added
between VTT_IN and VDDQ.
(12) VTTS
VTTS is to improve load regulation of VTT output. For precise load regulation, VTTS is connected close by VTT to avoid
common impedance.
(Example)
(13) Please add a protection diode when a large inductance component is
OUTPUT PIN
connected to the output terminal, and reverse-polarity power is possible at
startup or in output OFF condition.
REV. B
Appendix
Notes
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The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you
wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM
upon request.
Examples of application circuits, circuit constants and any other information contained herein illustrate the
standard usage and operations of the Products. The peripheral conditions must be taken into account
when designing circuits for mass production.
Great care was taken in ensuring the accuracy of the information specified in this document. However, should
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sponsibility for such damage.
The technical information specified herein is intended only to show the typical functions of and examples
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