74ALVC164245
16-bit dual supply translating transceiver; 3-state
Rev. 8 — 15 March 2012
Product data sheet
1. General description
The 74ALVC164245 is a high-performance, low-power, low-voltage, Si-gate CMOS
device, superior to most advanced CMOS compatible TTL families.
The 74ALVC164245 is a 16-bit (dual octal) dual supply translating transceiver featuring
non-inverting 3-state bus compatible outputs in both send and receive directions. It is
designed to interface between a 3 V and 5 V bus in a mixed 3 V and 5 V supply
environment.
This device can be used as two 8-bit transceivers or one 16-bit transceiver.
The direction control inputs (1DIR and 2DIR) determine the direction of the data flow.
nDIR (active HIGH) enables data from nAn ports to nBn ports. nDIR (active LOW) enables
data from nBn ports to nAn ports. The output enable inputs (1OE and 2OE), when HIGH,
disable both nAn and nBn ports by placing them in a high-impedance OFF-state. Pins
nAn, nOE and nDIR are referenced to V
CC(A)
and pins nBn are referenced to V
CC(B)
.
In suspend mode, when one of the supply voltages is zero, there will be no current flow
from the non-zero supply towards the zero supply. The nAn-outputs must be set 3-state
and the voltage on the A-bus must be smaller than V
diode
(typical 0.7 V). V
CC(B)
V
CC(A)
(except in suspend mode).
2. Features and benefits
5 V tolerant inputs/outputs for interfacing with 5 V logic
Wide supply voltage range:
3 V port (V
CC(A)
): 1.5 V to 3.6 V
5 V port (V
CC(B)
): 1.5 V to 5.5 V
CMOS low power consumption
Direct interface with TTL levels
Control inputs voltage range from 2.7 V to 5.5 V
Inputs accept voltages up to 5.5 V
High-impedance outputs when V
CC(A)
or V
CC(B)
= 0 V
Complies with JEDEC standard JESD8-B/JESD36
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Specified from
40 C
to +85
C
and
40 C
to +125
C
NXP Semiconductors
74ALVC164245
16-bit dual supply translating transceiver; 3-state
3. Ordering information
Table 1.
Ordering information
Temperature
range
40 C
to +125
C
Package
Name
SSOP48
TSSOP48
HXQFN60
Description
plastic shrink small outline package; 48 leads;
body width 7.5 mm
Version
SOT370-1
Type number
74ALVC164245DL
74ALVC164245DGG
40 C
to +125
C
74ALVC164245BX
40 C
to +125
C
plastic thin shrink small outline package; 48 leads; SOT362-1
body width 6.1 mm
plastic compatible thermal enhanced extremely
thin quad flat package; no leads; 60 terminals;
body 4
6
0.5 mm
SOT1134-2
4. Functional diagram
1DIR
1OE
1A0
1B0
1A1
1B1
1A2
1B2
1A3
1B3
1A4
1B4
1A5
1B5
1A6
1B6
1A7
1B7
2DIR
2OE
2A0
2B0
2A1
2B1
2A2
2B2
2A3
2B3
2A4
2B4
2A5
2B5
2A6
2B6
2A7
2B7
001aaa789
Fig 1.
Logic symbol
74ALVC164245
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 8 — 15 March 2012
2 of 20
NXP Semiconductors
74ALVC164245
16-bit dual supply translating transceiver; 3-state
terminal 1
index area
D1
A32
A31
A30
A29
A28
A27
D4
A1
D5
B20
B19
B18
D8
A26
A2
B1
A3
B2
A4
B3
A5
B4
A6
B5
A7
B6
A8
B7
A9
GND
(1)
B11
B12
B13
B15
B16
B17
A25
A24
A23
A22
74ALVC164245
B14
A21
A20
A19
A18
A10
D6
B8
B9
B10
D7
A17
D2
A11
A12
A13
A14
A15
A16
D3
001aai851
Transparent top view
(1) This is not a supply pin, the substrate is attached to this pad using conductive die attach material. There is no electrical or
mechanical requirement to solder this pad however if it is soldered the solder land should remain floating or be connected to
GND.
Fig 4.
Pin configuration SOT1134-2 (HXQFN60)
74ALVC164245
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 8 — 15 March 2012
5 of 20
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