Advance
‡
134b: x32 Automotive LPDDR2 SDRAM
Features
Automotive LPDDR2 SDRAM
MT42L16M32D1
Features
• Ultra low-voltage core and I/O power supplies
– V
DD2
= 1.14–1.30V
– V
DDCA
/V
DDQ
= 1.14–1.30V
– V
DD1
= 1.70–1.95V
• Clock frequency range
– 533–10 MHz (data rate range: 1066–20 Mb/s/pin)
• Four-bit prefetch DDR architecture
• Eight internal banks for concurrent operation
• Multiplexed, double data rate, command/address
inputs; commands entered on every CK edge
• Bidirectional/differential data strobe per byte of
data (DQS/DQS#)
• Programmable READ and WRITE latencies (RL/WL)
• Programmable burst lengths: 4, 8, or 16
• Per-bank refresh for concurrent operation
• On-chip temperature sensor to control self refresh
rate (SR not supported >105°C)
• Partial-array self refresh (PASR)
• Deep power-down mode (DPD)
• Selectable output drive strength (DS)
• Clock stop capability
• RoHS-compliant, “green” packaging
• AEC-Q100
Table 1: Key Timing Parameters
Speed
Grade
-18
Clock Rate
(MHz)
533
Data Rate
(Mb/s/pin)
1066
RL
8
WL
4
Options
• V
DD2
: 1.2V
• Configuration
– 4 Meg x 32 x 4 banks
• Device type
– LPDDR2-S4, 1 die in package
• FBGA “green” package
– 134-ball FBGA
(10mm x 11.5mm)
• Timing – cycle time
– 1.875ns @ RL = 8
• Special options
– Automotive grade (Package-level
burn-in)
• Operating temperature range
1
– From –40°C to +105°C
– From –40°C to +125°C
• Revision
Notes:
Marking
L
16M32
D1
HE
-18
A
AT
UT
2
E
1. When T
C
>105°C, self refresh mode is not
available.
2. UT option use based on automotive usage
model. Contact Micron sales representative
with questions.
Table 2: S4 Configuration Addressing
Architecture
Die configuration
Row addressing
Column addressing
Number of die
Die per rank
Ranks per channel
1
Note:
16 Meg x 32
4 Meg x 32 x 4 banks
8K (A[12:0])
512 (A[8:0])
1
1
1
1. A channel is a complete LPDRAM interface, including command/address and data pins.
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‡Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by
Micron without notice. Products are only warranted by Micron to meet Micron's production data sheet specifications.
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2020 Micron Technology, Inc. All rights reserved.
Advance
134b: x32 Automotive LPDDR2 SDRAM
Features
Figure 1: LPDDR2 Part Numbering
MT
42
L
16M32
D1
HE
-18
A
AT
:E
Micron Technology
Product Family
42 = Mobile LPDDR2 SDRAM
Design Revision
:E = Fifth generation
Operating Temperature
AT = –40°C to +105°C
UT = –40°C to +125°C
Operating Voltage
L = 1.2V
Automotive Certified
Configuration
16M32 = 16 Meg x 32
A = Package-level burn-in
Cycle Time
-18 = 1.875ns,
t
CK RL = 8
D1 = LPDDR2, 1 die
Addressing
Package Codes
HE = 134-ball FBGA, 10mm x 11.5mm
FBGA Part Marking Decoder
Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the
part number. Micron’s FBGA part marking decoder is available at www.micron.com/decoder.
Table 3: Package Codes and Descriptions
Package
Code
HE
Notes:
Ball Count
134
# Ranks
1
# Channels Size (mm)
1
10 x 11.5 x 1.0, 0.65 pitch
Die per
Package
SDP
Solder Ball
Composition
SAC302
1. SDP = Single-die package
2. Solder ball material: SAC302 (96.8% Sn, 3% Ag, 0.2% Cu).
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134b: x32 Automotive LPDDR2 SDRAM
Features
Contents
Important Notes and Warnings ......................................................................................................................... 9
General Description ....................................................................................................................................... 10
General Notes ............................................................................................................................................ 10
I
DD
Specifications ........................................................................................................................................... 11
Package Block Diagrams ................................................................................................................................. 14
Package Dimensions ....................................................................................................................................... 15
Ball Assignments ............................................................................................................................................ 16
Ball Descriptions ............................................................................................................................................ 17
Functional Description ................................................................................................................................... 18
Power-Up ....................................................................................................................................................... 19
Initialization After RESET (Without Voltage Ramp) ...................................................................................... 21
Power-Off ....................................................................................................................................................... 21
Uncontrolled Power-Off .............................................................................................................................. 22
Mode Register Definition ................................................................................................................................ 22
Mode Register Assignments and Definitions ................................................................................................ 22
ACTIVATE Command ..................................................................................................................................... 33
8-Bank Device Operation ............................................................................................................................ 33
Read and Write Access Modes ......................................................................................................................... 34
Burst READ Command ................................................................................................................................... 34
READs Interrupted by a READ ..................................................................................................................... 41
Burst WRITE Command .................................................................................................................................. 41
WRITEs Interrupted by a WRITE ................................................................................................................. 44
BURST TERMINATE Command ...................................................................................................................... 44
Write Data Mask ............................................................................................................................................. 46
PRECHARGE Command ................................................................................................................................. 47
READ Burst Followed by PRECHARGE ......................................................................................................... 48
WRITE Burst Followed by PRECHARGE ....................................................................................................... 49
Auto Precharge ........................................................................................................................................... 50
READ Burst with Auto Precharge ................................................................................................................. 50
WRITE Burst with Auto Precharge ............................................................................................................... 51
REFRESH Command ...................................................................................................................................... 53
REFRESH Requirements ............................................................................................................................. 59
SELF REFRESH Operation ............................................................................................................................... 61
Partial-Array Self Refresh – Bank Masking .................................................................................................... 62
Partial-Array Self Refresh – Segment Masking .............................................................................................. 63
MODE REGISTER READ ................................................................................................................................. 64
Temperature Sensor ................................................................................................................................... 66
DQ Calibration ........................................................................................................................................... 68
MODE REGISTER WRITE Command ............................................................................................................... 70
MRW RESET Command .............................................................................................................................. 70
MRW ZQ Calibration Commands ................................................................................................................ 71
ZQ External Resistor Value, Tolerance, and Capacitive Loading ..................................................................... 73
Power-Down .................................................................................................................................................. 73
Deep Power-Down ......................................................................................................................................... 80
Input Clock Frequency Changes and Stop Events ............................................................................................. 81
Input Clock Frequency Changes and Clock Stop with CKE LOW ................................................................... 81
Input Clock Frequency Changes and Clock Stop with CKE HIGH .................................................................. 82
NO OPERATION Command ............................................................................................................................ 82
Simplified Bus Interface State Diagram ........................................................................................................ 82
Truth Tables ................................................................................................................................................... 84
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134b: x32 Automotive LPDDR2 SDRAM
Features
Electrical Specifications .................................................................................................................................. 92
Absolute Maximum Ratings ........................................................................................................................ 92
Input/Output Capacitance .......................................................................................................................... 92
Electrical Specifications – I
DD
Specifications and Conditions ............................................................................ 93
AC and DC Operating Conditions .................................................................................................................... 96
AC and DC Logic Input Measurement Levels for Single-Ended Signals .............................................................. 98
V
REF
Tolerances .......................................................................................................................................... 99
Input Signal .............................................................................................................................................. 100
AC and DC Logic Input Measurement Levels for Differential Signals ................................................................ 102
Single-Ended Requirements for Differential Signals .................................................................................... 103
Differential Input Crosspoint Voltage ......................................................................................................... 105
Input Slew Rate ......................................................................................................................................... 105
Output Characteristics and Operating Conditions ........................................................................................... 106
Single-Ended Output Slew Rate .................................................................................................................. 107
Differential Output Slew Rate ..................................................................................................................... 108
HSUL_12 Driver Output Timing Reference Load ......................................................................................... 111
Output Driver Impedance .............................................................................................................................. 111
Output Driver Impedance Characteristics with ZQ Calibration .................................................................... 112
Output Driver Temperature and Voltage Sensitivity ..................................................................................... 113
Output Impedance Characteristics Without ZQ Calibration ......................................................................... 113
Clock Specification ........................................................................................................................................ 116
t
CK(abs),
t
CH(abs), and
t
CL(abs) ................................................................................................................ 117
Clock Period Jitter .......................................................................................................................................... 117
Clock Period Jitter Effects on Core Timing Parameters ................................................................................. 117
Cycle Time Derating for Core Timing Parameters ........................................................................................ 118
Clock Cycle Derating for Core Timing Parameters ....................................................................................... 118
Clock Jitter Effects on Command/Address Timing Parameters ..................................................................... 118
Clock Jitter Effects on READ Timing Parameters .......................................................................................... 118
Clock Jitter Effects on WRITE Timing Parameters ........................................................................................ 119
Refresh Requirements .................................................................................................................................... 120
AC Timing ..................................................................................................................................................... 121
CA and CS# Setup, Hold, and Derating ........................................................................................................... 127
Data Setup, Hold, and Slew Rate Derating ....................................................................................................... 134
Revision History ............................................................................................................................................ 141
Rev. C – 02/20 ............................................................................................................................................ 141
Rev. B – 02/20 ............................................................................................................................................ 141
Rev. A – 01/20 ............................................................................................................................................ 141
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Advance
134b: x32 Automotive LPDDR2 SDRAM
Features
List of Figures
Figure 1: LPDDR2 Part Numbering ................................................................................................................... 2
Figure 2: V
DD1
Typical Self-Refresh Current vs. Temperature ............................................................................ 13
Figure 3: V
DD2
Typical Self-Refresh Current vs. Temperature ............................................................................ 13
Figure 4: Single Die, Single Rank, Single Channel Package Block Diagram ........................................................ 14
Figure 5: 134-Ball VFBGA – 10mm x 11.5mm (Package Code: HE) .................................................................... 15
Figure 6: 134-Ball FBGA (16 Meg x 32) ............................................................................................................ 16
Figure 7: Functional Block Diagram ............................................................................................................... 18
Figure 8: Voltage Ramp and Initialization Sequence ........................................................................................ 21
Figure 9: ACTIVATE Command ...................................................................................................................... 33
Figure 10:
t
FAW Timing (8-Bank Devices) ....................................................................................................... 34
Figure 11: READ Output Timing –
t
DQSCK (MAX) ........................................................................................... 35
Figure 12: READ Output Timing –
t
DQSCK (MIN) ........................................................................................... 35
Figure 13: Burst READ – RL = 5, BL = 4,
t
DQSCK >
t
CK ..................................................................................... 36
Figure 14: Burst READ – RL = 3, BL = 8,
t
DQSCK <
t
CK ..................................................................................... 36
Figure 15:
t
DQSCKDL Timing ........................................................................................................................ 37
Figure 16:
t
DQSCKDM Timing ....................................................................................................................... 38
Figure 17:
t
DQSCKDS Timing ......................................................................................................................... 39
Figure 18: Burst READ Followed by Burst WRITE – RL = 3, WL = 1, BL = 4 ......................................................... 40
Figure 19: Seamless Burst READ – RL = 3, BL = 4,
t
CCD = 2 .............................................................................. 40
Figure 20: READ Burst Interrupt Example – RL = 3, BL = 8,
t
CCD = 2 ................................................................. 41
Figure 21: Data Input (WRITE) Timing ........................................................................................................... 42
Figure 22: Burst WRITE – WL = 1, BL = 4 ......................................................................................................... 42
Figure 23: Burst WRITE Followed by Burst READ – RL = 3, WL = 1, BL = 4 ......................................................... 43
Figure 24: Seamless Burst WRITE – WL = 1, BL = 4,
t
CCD = 2 ............................................................................ 43
Figure 25: WRITE Burst Interrupt Timing – WL = 1, BL = 8,
t
CCD = 2 ................................................................ 44
Figure 26: Burst WRITE Truncated by BST – WL = 1, BL = 16 ............................................................................ 45
Figure 27: Burst READ Truncated by BST – RL = 3, BL = 16 ............................................................................... 46
Figure 28: Data Mask Timing ......................................................................................................................... 46
Figure 29: Write Data Mask – Second Data Bit Masked .................................................................................... 47
Figure 30: READ Burst Followed by PRECHARGE – RL = 3, BL = 8, RU(
t
RTP(MIN)/
t
CK) = 2 ................................ 48
Figure 31: READ Burst Followed by PRECHARGE – RL = 3, BL = 4, RU(
t
RTP(MIN)/
t
CK) = 3 ................................ 49
Figure 32: WRITE Burst Followed by PRECHARGE – WL = 1, BL = 4 .................................................................. 50
Figure 33: READ Burst with Auto Precharge – RL = 3, BL = 4, RU(
t
RTP(MIN)/
t
CK) = 2 ........................................ 51
Figure 34: WRITE Burst with Auto Precharge – WL = 1, BL = 4 .......................................................................... 52
Figure 35: Regular Distributed Refresh Pattern ............................................................................................... 56
Figure 36: Supported Transition from Repetitive REFRESH Burst .................................................................... 57
Figure 37: Nonsupported Transition from Repetitive REFRESH Burst .............................................................. 58
Figure 38: Recommended Self Refresh Entry and Exit ..................................................................................... 59
Figure 39:
t
SRF Definition .............................................................................................................................. 60
Figure 40: All-Bank REFRESH Operation ........................................................................................................ 60
Figure 41: Per-Bank REFRESH Operation ....................................................................................................... 61
Figure 42: SELF REFRESH Operation .............................................................................................................. 62
Figure 43: MRR Timing – RL = 3,
t
MRR = 2 ...................................................................................................... 64
Figure 44: READ to MRR Timing – RL = 3,
t
MRR = 2 ......................................................................................... 65
Figure 45: Burst WRITE Followed by MRR – RL = 3, WL = 1, BL = 4 ................................................................... 66
Figure 46: Temperature Sensor Timing ........................................................................................................... 68
Figure 47: MR32 and MR40 DQ Calibration Timing – RL = 3,
t
MRR = 2 ............................................................. 69
Figure 48: MODE REGISTER WRITE Timing – RL = 3,
t
MRW = 5 ....................................................................... 70
Figure 49: ZQ Timings ................................................................................................................................... 72
Figure 50: Power-Down Entry and Exit Timing ................................................................................................ 74
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