AF2302N
20V N-Channel Enhancement Mode MOSFET
Features
- Advanced trench process technology
- High density cell design for ultra low on-resistance
- Excellent thermal and electrical capabilities
- Compact and low profile SOT-23 package
Product Summary
V
DS
= 20V
R
DS (on)
, V
GS
@4.5V, I
DS
@3.6A =65mΩ.
R
DS (on)
, V
GS
@2.5V, I
DS
@3.1A =95mΩ.
Pin Assignments
3
(Top View)
1. G
2. S
3. D
Pin Descriptions
Pin
No.
1
2
3
Pin
Name
G
S
D
Description
Gate
Source
Drain
1
2
Ordering information
A X
Feature
F :MOSFET
PN
2302N X X X
Package
W: SOT23
Lead Free
Blank : Normal
L : Lead Free Package
Packing
Blank : Tube or Bulk
A : Tape & Reel
Block Diagram
D
S
G
This datasheet contains new product information. Anachip Corp. reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of
this product. No rights under any patent accompany the sale of the product.
Rev. 1.1 Jul 20, 2004
1/4
AF2302N
20V N-Channel Enhancement Mode MOSFET
Absolute Maximum Ratings
(T
A
=25ºC unless otherwise noted)
Symbol
V
DS
V
GS
I
D
I
DM
P
D
T
J
T
J
, T
STG
Parameter
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain Current
Pulsed Drain Current
Maximum Power Dissipation
T
A
=25ºC
T
A
=70ºC
Operating Junction Temperature
Operating Junction and Storage Temperature Range
Rating
20
±8
2.4
10
1.25
0.8
+150
-55 to +150
Units
V
V
A
A
W
ºC
ºC
Thermal Performance
Symbol
T
L
R
θJA
Parameter
Lead Temperature (1/8” from case)
Junction to Ambient Thermal Resistance (PCB mounted)
Limit
5
100
Units
S
ºC/W
Note:
Surface mounted on FR4 board t < 5 sec.
Electrical Characteristics
Rate I
D
=2.4A, (T
A
=25
o
C unless otherwise noted)
Symbol
Static
BV
DSS
R
DS(ON)
Parameter
Drain-Source Breakdown Voltage
Drain-Source On-State Resistance
Test Conditions
V
GS
=0V, I
D
=250uA
V
GS
=4.5V, I
D
=3.6A
V
GS
=2.5V, I
D
=3.1A
V
DS
= V
GS
, I
D
=250uA
V
DS
=20V, V
GS
=0V
V
GS
=±8V, V
DS
=0V
V
DS
=5V, V
GS
=4.5V
V
DS
=5V, I
D
=3.6A
V
DS
=10V, I
D
=3.6A,
V
GS
=4.5V
V
DD
=10V, R
L
=10Ω,
I
D
=1A, V
GEN
=4.5V,
R
G
=6Ω
V
DS
=10V, V
GS
=0V,
f=1.0MHz
Min.
20
-
-
0.45
-
-
6
-
-
-
-
-
-
-
-
-
-
-
-
-
Limits
Typ.
-
50
75
-
-
-
-
10
5.2
0.65
1.5
7
55
16
10
450
70
43
-
0.75
Max.
-
65
95
-
1.0
±100
-
-
10
-
-
15
80
60
25
-
-
-
1.6
1.2
Unit
V
mΩ
V
uA
nA
A
S
V
GS(TH)
Gate Threshold Voltage
I
DSS
Zero Gate Voltage Drain Current
I
GSS
Gate Body Leakage
I
D(ON)
On-State Drain Current
g
fs
Forward Tranconductance
Dynamic
Q
g
Total Gate Charge
Q
gs
Gate-Source Charge
Q
gd
Gate-Drain Charge
t
d(on)
Turn-On Delay Time
t
r
Turn-On Rise Time
t
d(off)
Turn-Off Delay Time
t
f
Turn-Off Fall-Time
C
iss
Input Capacitance
C
oss
Output Capacitance
C
rss
Reverse Transfer Capacitance
Source-Drain Diode
I
S
Max. Diode Forward Current
V
SD
Diode Forward Voltage
Note:
Pulse test: pulse width < 300uS, duty cycle < 2%
nC
nS
pF
I
S
=1.0A, V
GS
=0V
A
V
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www.anachip.com.tw
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Rev. 1.1 Jul 20, 2004
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