1:8 Universal Differential Fanout
Buffer
8T79S308
Datasheet
Description
The 8T79S308 is a fully integrated signal fanout buffer for
high-performance, low additive phase noise applications. The
main function of the device is the distribution and fanout of
high-frequency clocks or low-frequency synchronization signals.
The 8T79S308 is optimized to deliver very low phase noise clocks
and precise, low-skew outputs, low device-to-device skew
characteristics and fast output rise/fall times help the system
design to achieve deterministic clock phase relationship across
devices.
The device distributes the input signals (IN_0, IN_1) to two fanout
banks. A input select logic allows the device to operate as
1:8 buffer, dual 1:4 buffers, and to cross the input signals.
The propagation delay in both outputs banks is designed for equal
delay to support fixed phase relationships between both banks. All
outputs are very flexible in LVPECL/LVDS output style
configuration, output signal termination, and allow both DC and
AC coupling. Outputs can be individually disabled through a serial
interface.
The device is packaged in a lead-free (RoHS 6) 40-VFQFPN
package. The extended temperature range supports wireless
infrastructure, telecommunication, and networking end equipment
requirements. The 8T79S308 is a member of the
high-performance clock family from IDT.
Features
▪
▪
▪
▪
High-performance, flexible clock/data/1PPS fanout buffer
Low phase noise floor: -160dBc/Hz (156.256MHz clock)
Integrated phase noise of < 65fs RMS typical (12kHz–20MHz)
Flexible input selection
•
1:8 Fanout modes
•
Dual 1:4 Buffer fanout modes
▪
Eight differential outputs, organized in two banks of four
outputs
▪
Low-power LVPECL/LVDS outputs support DC and AC
coupling and LVPECL, LVDS line terminations techniques
▪
Individually configured outputs through an I
2
C interface
•
LVPECL/LVDS output style, HCSL compatible (AC-coupled)
•
Output amplitude
•
Output enable
▪
Supported clock frequency range: 0 to 3GHz
▪
Core and output supply voltage modes:
•
3.3V core, 3.3V, 2.5V, and 1.8V output supply
•
2.5V core, 2.5V, and 1.8V output supply
▪
Selectable I
2
C I/O interface voltage: 1.8V and VDD
▪
Integrated low dropout regulators (LDOs) for excellent power
supply noise rejection
▪
Package: 6 × 6 mm 40-VFQFPN
Block Diagram
IN_0
nIN_0
VT_0
IN_1
nIN_1
VT_1
XSEL[1:0]
50 50
50 50
▪
Temperature range: -40°C to +105°C
QA0
nQA0
QA1
nQA1
QA2
nQA2
QA3
nQA3
Bank A
Typical Applications
▪
Wireless infrastructure applications: GSM, WCDMA, LTE,
LTE-A
POD_OE
SDA
SCL
VSEL_I2C
VSEL_VDD
ADR[2:0]
Bank B
I
2
C
Output
Enable
Register
QB0
nQB0
QB1
nQB1
QB2
nQB2
QB3
nQB3
▪
▪
▪
▪
▪
Ideal clock driver for jitter-sensitive ADC and DAC circuits
Low phase noise clock generation
Ethernet line cards
Radar and imaging
Instrumentation and medical
©2018 Integrated Device Technology, Inc
1
August 10, 2018
8T79S308 Datasheet
Contents
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Principles of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Voltage Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin Controlled Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Input Signal Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Device Information Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Device Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Pin Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Phase Noise Plots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Application Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Termination for Q, nQ LVDS Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
AC Termination for Q, nQ Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Termination for Q, nQ LVPECL Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Termination for Q, nQ LVPECL Outputs AC-Coupled into HCSL-Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Input Interface Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Temperature Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Package Outline Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Marking Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
©2018 Integrated Device Technology, Inc
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August 10, 2018
8T79S308 Datasheet
Pin Assignments
Figure 1. Pin Assignments (Top View)
VDDB
VDDB
31
30
29
28
27
nQB0
nQB1
nQB2
40
39
38
37
36
35
34
33
POD_OE
VSEL_I2C
XSEL0
XSEL1
VDD
SCL
SDA
ADR0
ADR1
ADR2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
nQB3
32
QB0
QB1
QB2
QB3
NC
IN_1
nIN_1
VT_1
VDD_IN_1
VDD_IN_0
VT_0
nIN_0
IN_0
VSEL_VDD
Exposed Pad
(GND)
26
25
24
23
22
21
Pin Descriptions
Table 1. Pin Descriptions
[a]
Pin
Name
Type
[b]
Signal Input Pins
Description
22
23
24
29
28
27
IN_0
nIN_0
VT_0
IN_1
nIN_1
VT_1
Input
Termination
Input
Termination
Device clock 0 inverting and non-inverting differential clock input. Internally
terminated 50Ω to VT_0. Compatible with LVPECL, LVDS signals.
Input for termination. Both IN_0 and nIN_0 inputs are internally terminated 50Ω to
this pin.
Device clock 1 inverting and non-inverting differential clock input. Internally
terminated 50Ω to VT_1. Compatible with LVPECL, LVDS signals.
Input for termination. Both IN_1 and nIN_1 inputs are internally terminated 50Ω to
this pin.
Signal Output Pins
12,
13
14,
15
16,
17
QA0,
nQA0
QA1,
nQA1
QA2,
nQA2
Output
Output
Output
Differential clock output A0 (Bank A). Configurable LVPECL/LVDS style.
Differential clock output A1 (Bank A). Configurable LVPECL/LVDS style.
Differential clock output A2 (Bank A). Configurable LVPECL/LVDS style.
©2018 Integrated Device Technology, Inc
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August 10, 2018
8T79S308 Datasheet
Table 1. Pin Descriptions
[a]
(Cont.)
Pin
18,
19
39,
38
37,
36
35,
34
33,
32
Name
QA3,
nQA3
QB0,
nQB0
QB1,
nQB1
QB2,
nQB2
QB3,
nQB3
Type
[b]
Output
Output
Output
Output
Output
Description
Differential clock output A3 (Bank A). Configurable LVPECL/LVDS style.
Differential clock output B0 (Bank B). Configurable LVPECL/LVDS style.
Differential clock output B1 (Bank B). Configurable LVPECL/LVDS style.
Differential clock output B2 (Bank B). Configurable LVPECL/LVDS style.
Differential clock output B3 (Bank B). Configurable LVPECL/LVDS style.
I
2
C Serial Interface Pins
6
SCL
Input
Input/
Output
Serial Control Port I
2
C Clock Input. Interface voltage is selected by the VSEL_I2C
pin. Input has hysteresis. Use an external pull-up resistor to the serial interface
supply voltage.
Serial Control Port I
2
C data I/O. Interface voltage is selected by the VSEL_I2C pin.
Input has hysteresis (when input). For output: open collector, use an external pull-up
resistor to the selected serial interface supply voltage
LVCMOS Control Function Pins
7
SDA
8
9
10
3
4
2
21
30
1
ADR0
ADR1
ADR2
XSEL_0
XSEL_1
VSEL_I2C
VSEL_VDD
NC
POD_OE
Input
Input
Input
Input
Input
Input
Input
-
Input
PD
PD
PD
PD
PD
PD
PD
Serial Control Port/I
2
C Address Bit 0, 1 and 2. LVCMOS interface levels are
determined by
V
DD_V
voltage.
Signal distribution select pins 0 and 1. LVCMOS interface levels are determined by
V
DD_V
voltage.
Interface voltage select for the I
2
C interface pins. LVCMOS interface levels are
determined by
V
DD_V
voltage.
Core supply voltage select. Set this pin to 0 or 1 according to the applied core
voltage (2.5V or 3.3V) of the device. LVCMOS interface levels.
No connect.
Power-on default output-enable state. LVCMOS interface levels are determined by
V
DD_V
voltage.
PD
Power Pins and Exposed Pad Connection
25
26
11, 20
31, 40
5
—
VDD_IN_0
VDD_IN_1
VDDA
VDDB
VDD
GND
Power
Power
Power
Power
Power
Power
Positive supply voltage (3.3V, 2.5V) for the IN_0/nIN_0 input.
Positive supply voltage (3.3V, 2.5V) for the IN_1/nIN_1 input.
Positive supply voltage (3.3V, 2.5V, 1.8V) for the QA[3:0] outputs.
Positive supply voltage (3.3V, 2.5V, 1.8V) for the QB[3:0] outputs.
Positive supply voltage (3.3V, 2.5V) for the device core functions.
Exposed pad: Ground supply voltage (GND) and ground return path. Connect to
board GND (0V).
[a] For essential information on power supply filtering, see
Application Information.
[b] PU (pull-up) and PD (pull-down) indicate internal input resistors (for values, see
Figure 13).
©2018 Integrated Device Technology, Inc
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August 10, 2018
8T79S308 Datasheet
Principles of Operation
Overview
The 8T79S308 is designed for low phase noise and skew critical differential clock distribution systems and supports clock frequencies
from 1PPS up to 3GHz. An input-to-output cross-connect, individually configurable LVPECL/LVDS outputs, amplitude settings and output
enable make this device very flexible. The power-up default output enable state can be set by an dedicated control input. An I
2
C interface
is available for individual output configurations. The signal voltage level of the I
2
C interface pins is configurable to 1.8V and 2.5V/3.3V
voltage supply. The configurable I
2
C slave address pins are available to allow up to eight devices on the same I
2
C bus.
Signal flow:
The device can be configured as single 1:8 or dual 1:4 buffer with selectable IN_0 and IN_1 inputs as signal source,
controlled by the XSEL[1:0] configuration input.
The
output style
state of each individual differential output Q, nQ can be set by the content the I
2
C register 0x10 (see
Table 10).
A logic
zero to an I
2
C bit in register 0x10 sets corresponding differential output to LVPECL, while a logic one sets the differential output to LVDS
(see
Table 11).
Register 0x10 resets to logic 0 (all outputs: LVPECL) at each power-up. Setting and changing the output style through the
I
2
C interface is asynchronous to the input reference clock.
The
output amplitude
of each individual differential output Q, nQ can be set by the content of the I
2
C registers 0x11–0x12 (see
Table 11).
For LVPECL outputs, the device supports amplitude settings of 500mV and 750mV; for LVDS outputs, 350mV and 500mV are
supported. Register 0x11-0x12 reset to logic 0 (LVPECL standard amplitude) at each power-up. Setting and changing the output style
through the I
2
C interface is asynchronous to the input reference clock. For LVPECL, the output termination has to be adjusted for the
selected amplitude.
The
output enable/disable state
of each individual differential output Q, nQ can be set by the content of I
2
C register 0x13
(see
Table 11).
A logic zero to an I
2
C bit in register 0x02 disables the corresponding differential output in high-impedance state, while a
logic one enables the differential output (see
Table 11).
After each power cycle, the device copies the state of the POD_OE input into all
eight bits (D7-0) of register 0x13 to: If pin POD_OE = 0 or open, the device powers up with all outputs disabled in high-impedance state,
if pin POD_OE=1, the device powers up with all outputs enabled. After the first valid I
2
C write, the output enable state is controlled by the
I
2
C register 0x13. Setting and changing the output enable state through the I
2
C interface is asynchronous to the input reference clock.
Voltage Supply
Table 2. Supported Voltage Supply Operations
Core Supply
V
DD_V
[a][b]
3.3V
2.5V
Output Supply
V
DD_O
[c][d]
3.3V, 2.5V, 1.8V
2.5V, 1.8V
[a] V
DD_V
denominates V
DD
, V
DD_IN_1
, V
DD_IN_0.
I
2
C interface levels are configured by the VSEL_I2C pin.
[b] V
DD_V
core supply voltages must be equal: V
DD
= V
DD_IN_0
= V
DD_IN_1.
[c] V
DD_O
denominates V
DDA
and V
DDB.
V
DD_V
≥
V
DD_O.
[d] V
DDA
= V
DDB
and V
DDA
≠
V
DDB
are both supported voltage operations.
©2018 Integrated Device Technology, Inc
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August 10, 2018
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