ZL30407
SONET/SDH Network Element PLL
Data Sheet
Features
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•
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•
•
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•
•
•
Meets requirements of GR-253 for SONET
Stratum 3 and SONET Minimum Clocks (SMC)
Meets requirements of GR-1244 for Stratum 3
Meets requirements of G.813 Option 1 and 2 for
SDH Equipment Clocks (SEC)
Generates clocks for ST-BUS, DS1, DS2, DS3,
OC-3, E1, E3, STM-1 and 19.44 MHz
Meets holdover accuracy of GR-1244 Stratum 3E
and ITU-T G.812 (better than 1x10
-12
)
Continuously monitors both references for
frequency accuracy exceeding ±12 ppm
Provides “hit-less” reference switching
Compensates for Master Clock Oscillator
accuracy
Detects frequency of both reference clocks and
synchronizes to any combination of 8 kHz, 1.544
MHz, 2.048 MHz and 19.44 MHz reference
frequencies.
Allows Hardware or Microprocessor control
Pin compatible with ZL30402 and MT90401.
Ordering Information
ZL30407/QCC 80 Pin LQFP
-40°C to +85°C
April 2003
Description
The ZL30407 is a Network Element Phase-Locked
Loop designed to synchronize SDH and SONET
systems. In addition, it generates multiple clocks for
legacy PDH equipment and provides timing for ST-BUS
and GCI backplanes.
The ZL30407 operates in NORMAL (LOCKED),
HOLDOVER and FREE-RUN modes to ensure that in
the presence of jitter, wander and interruptions to the
reference signals, the generated clocks meet
international standards. The filtering characteristics of
the PLL are hardware or software selectable and they
do not require any external adjustable components.
The ZL30407 uses an external 20 MHz Master Clock
Oscillator to provide a stable timing source for the
HOLDOVER operation.
The ZL30407 operates from a single 3.3 V power
supply and offers a 5 V tolerant microprocessor
interface.
FCS
OE
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•
Applications
•
•
Synchronization for SDH and SONET Network
Elements
Clock generation for ST-BUS and GCI backplanes
VDD GND
C20i
PRI
PRIOR
Primary
Acquisition
PLL
Master Clock
Frequency
Calibration
APLL
MUX
SEC
SECOR
RefSel
HW
RESET
CS DS R/W A0-A6 D0-D7
Core PLL
Clock
Synthesizer
Secondary
Acquisition
PLL
C155P/N
C34/C44
C19o
C16o
C8o
C6o
C4o
C2o
C1.5o
F16o
F8o
F0o
E3DS3/OC3
E3/DS3
Microport
Control State Machine
JTAG
IEEE
1149.1a
Tclk
Tdi
Tdo
Tms
Trst
M02
MS1 MS2
RefAlign LOCK HOLDOVER
Figure 1 - Functional Block Diagram
1
ZL30407
Table of Contents
Data Sheet
1.0 ZL30407 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.1 Pin Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.0 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
2.1 Acquisition PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2 Core PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2.1 Digitally Controlled Oscillator (DCO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2.2 Filters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2.3 Lock Indicator (LOCK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2.4 Reference Alignment (RefAlign) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.3 Clock Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.3.1 Output Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.3.2 Output Clocks Phase Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.4 Control State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.4.1 Clock Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.4.2 ZL30407 State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.4.3 State Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.5 Master Clock Frequency Calibration Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.6 Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.7 JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.0 Hardware and Software Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
3.1 Hardware Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.1 Control Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.2 Status Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 Software Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.1 Control Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.2 ZL30407 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.3 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1 ZL30407 Mode Switching - Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.1 System Start-up Sequence: FREE-RUN --> HOLDOVER --> NORMAL . . . . . . . . . . . . . . . . . . . .
4.1.2 Single Reference Operation: NORMAL --> AUTO HOLDOVER --> NORMAL . . . . . . . . . . . . . . . .
4.1.3 Dual Reference Operation: NORMAL --> AUTO HOLDOVER--> HOLDOVER --> NORMAL . . . .
4.1.4 Reference Switching (RefSel): NORMAL --> HOLDOVER --> NORMAL . . . . . . . . . . . . . . . . . . . .
4.2 Programming Master Clock Oscillator Frequency Calibration Register . . . . . . . . . . . . . . . . . . . . . . . . . .
18
19
20
20
20
21
22
31
31
32
33
34
35
4.0 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
5.0 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
5.1 AC and DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.2 Performance Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
2
Zarlink Semiconductor Inc.
Data Sheet
1.0
1.1
ZL30407
ZL30407 Pinout
Pin Connections
IC
DS
NC
LOCK
NC
HOLDOVER
VDD
C34/C44
GND
C20i
NC
VDD
RefAlign
RefSel
C19o
GND
IC
C6o
C1.5o
PRIOR
60
62
64
36
66
34
68
32
70
72
74
26
76
24
78
22
80
2
4
6
8
10
12
14
16
18
20
58
56
54
52
50
48
46
44
42 40
38
SECOR
OE
CS
RESET
HW
D0
D1
D2
D3
GND
IC
IC
VDD
D4
D5
D6
D7
R/W
A0
IC
ZL30407
30
28
NC
NC
Tdi
Trst
Tclk
Tms
Tdo
NC
GND
C155P
C155N
VDD
AVDD
GND
IC
GND
PRI
SEC
E3/DS3
E3DS3/OC3
IC
A1
A2
A3
A4
GND
A5
A6
FCS
VDD
GND
F16o
C16o
C8o
C4o
C2o
F0o
Figure 2 - Pin Connections for 80-pin LQFP package
Zarlink Semiconductor Inc.
MS1
MS2
F8o
3
ZL30407
Pin Description
Pin #
1
2-5
6
7-8
9
Name
IC
A1-A4
GND
A5-A6
FCS
Description
Internal Connection.
Leave unconnected.
Data Sheet
Address 1 to 4
(5 V tolerant input). Address inputs for the parallel processor
interface. Connect to ground in Hardware Control.
Ground.
Negative power supply.
Address 5 to 6
(5 V tolerant input). Address inputs for the parallel processor
interface. Connect to ground in Hardware Control.
Filter Characteristic Select
(Input). In Hardware Control, FCS selects the
filtering characteristics of the ZL30407. Set this pin high to have a loop filter
corner frequency of 0.1 Hz and limit the phase slope to 885 ns/sec. Set this pin
low to have corner frequency of 1.5 Hz and limit the phase slope to 41 ns per
1.326 ms. Connect to ground in Software Control. This pin is internally pulled
down to GND.
Positive Power Supply.
Ground.
Frame Pulse ST-BUS 8.192 Mb/s
(CMOS tristate output). This is an 8 kHz,
61ns wide, active low framing pulse, which marks beginning of a ST-BUS
frame. This frame pulse is typically used for ST-BUS operation at 8.192 Mb/s.
Clock 16.384 MHz
(CMOS tristate output). This clock is used for ST-BUS
operation at 8.192 Mb/s.
Clock 8.192 MHz
(CMOS tristate output). This clock is used for ST-BUS
operation at 8.192 Mb/s.
Clock 4.096 MHz
(CMOS tristate output). This clock is used for ST-BUS
operation at 2.048 Mb/s.
Clock 2.048 MHz
(CMOS tristate output). This clock is used for ST-BUS
operation at 2.048 Mb/s.
Frame Pulse ST-BUS 2.048 Mb/s
(CMOS tristate output). This is an 8 kHz,
244ns, active low framing pulse, which marks the beginning of a ST-BUS
frame. This is typically used for ST-BUS operation at 2.048 Mb/s and 4.096
Mb/s.
Mode Select 1
(Input). The MS1 and MS2 pins select the ZL30407 mode of
operation (Normal, Holdover or Free-run), see Table 1 on page 19 for details.
The logic level at this input is sampled by the rising edge of the F8o frame
pulse. Connect to ground in Software Control.
Mode Select 2
(Input). The MS2 and MS1 pins select the ZL30407 mode of
operation (Normal, Holdover or Free-run), see Table 1 on page 19 for details.
The logic level at this input is sampled by the rising edge of the F8o frame
pulse. Connect to ground in Software Control.
10
11
12
VDD
GND
F16o
13
14
15
16
17
C16o
C8o
C4o
C2o
F0o
18
MS1
19
MS2
4
Zarlink Semiconductor Inc.
Data Sheet
Pin Description (continued)
Pin #
20
Name
F8o
Description
ZL30407
Frame Pulse ST-BUS/GCI 8.192 Mb/s
(CMOS tristate output). This is an 8
kHz, 122 ns, active high framing pulse, which marks the beginning of a
ST-BUS/GCI frame. This is typically used for ST-BUS/GCI operation at 8.192
Mb/s. See Figure 15 for details.
E3DS3 or OC3 Selection
(Input). In Hardware Control, a logic low on this pin
enables the C155P/N outputs (pin 30 and pin 31) and sets the C34/C44 output
(pin 53) to provide C8 or C11 clocks. Logic high at this input disables the C155
clock outputs (high impedance) and sets C34/C44 output to provide C34 and
C44 clocks. In Software Control connect this pin to ground.
E3 or DS3 Selection
(Input). In Hardware Control, when the E3DS3/OC3 pin
is set high, logic low on E3/DS3 pin selects a 44.736 MHz clock on C34/C44
output and logic high selects 34.368 MHz clock. When E3DS3/OC3 pin is set
low, logic low on E3/DS3 pin selects 11.184 MHz clock on C34/C44 output and
logic high selects 8.592 MHz clock. Connect this input to ground in Software
Control.
Secondary Reference
(Input). This input is used as a secondary reference
source for synchronization. The ZL30407 can synchronize to the falling edge
of the 8 kHz, 1.544 MHz or 2.048 MHz clocks and the rising edge of the 19.44
MHz clock. In Hardware Control, selection of the input reference is based upon
the RefSel control input. This pin is internally pulled up to VDD.
Primary Reference
(Input). This input is used as a primary reference source
for synchronization. The ZL30407 can synchronize to the falling edge of the 8
kHz, 1.544 MHz or 2.048 MHz clocks and the rising edge of the 19.44 MHz
clock. In Hardware Control, selection of the input reference is based upon the
RefSel control input. This pin is internally pulled up to VDD.
Ground.
Internal Connection.
Leave unconnected.
Ground.
Positive Analog Power Supply.
Connect this pin to VDD.
Positive Power Supply.
Clock 155.52MHz
(LVDS output). Differential outputs for the 155.52 MHz
clock. These outputs are enabled by applying logic low to E3DS3/OC3 input or
they can be disabled by applying logic high. In the disabled state the LVDS
outputs are internally terminated with an integrated 100Ω resistor (two 50Ω
resistors connected in series). The middle point of these resistors is internally
biased from a 1.25V LVDS bias source.
Ground.
No internal bonding Connection.
Leave unconnected.
21
E3DS3/OC3
22
E3/DS3
23
SEC
24
PRI
25
26
27
28
29
30
31
GND
IC
GND
AVDD
VDD
C155N
C155P
32
33
GND
NC
Zarlink Semiconductor Inc.
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