HM62V8512BLTT-8 datasheet, PDF

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HM62V8512BLTT-8: Description4 M SRAM (512-kword x 8-bit); Categorystorage storage; File Size83KB，17 Pages; ManufacturerHitachi （Renesas ）; Websitehttp://www.renesas.com/eng/

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HM62V8512BLTT-8 Overview

4 M SRAM (512-kword x 8-bit)

HM62V8512BLTT-8 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Hitachi （Renesas ）
Parts packaging code	TSOP2
package instruction	TSOP2, TSOP32,.46
Contacts	32
Reach Compliance Code	unknow
Maximum access time	85 ns
I/O type	COMMON
JESD-30 code	R-PDSO-G32
JESD-609 code	e0
length	20.95 mm
memory density	4194304 bi
Memory IC Type	STANDARD SRAM
memory width	8
Number of functions	1
Number of terminals	32
word count	524288 words
character code	512000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature	-20 °C
organize	512KX8
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	TSOP2
Encapsulate equivalent code	TSOP32,.46
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE
Parallel/Serial	PARALLEL
power supply	3 V
Certification status	Not Qualified
Maximum seat height	1.2 mm
Minimum standby current	2 V
Maximum slew rate	0.04 mA
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	2.7 V
Nominal supply voltage (Vsup)	3 V
surface mount	YES
technology	CMOS
Temperature level	OTHER
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
width	10.16 mm

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HM62V8512B Series

4 M SRAM (512-kword

8-bit)

ADE-203-905G (Z)

Rev. 6.0

Mar. 31, 2000

Description

The Hitachi HM62V8512B is a 4-Mbit static RAM organized 512-kword

8-bit. It realizes higher density,

higher performance and low power consumption by employing 0.35

µm

Hi-CMOS process technology. The

device, packaged in a 525-mil SOP (foot print pitch width) or 400-mil TSOP TYPE II is available for high

density mounting. The HM62V8512B is suitable for battery backup system.

Features

•

Single 3.0 V supply: 2.7 V to 3.6 V

•

Access time: 70/85 ns (max)

•

Power dissipation



Active: 15 mW/MHz (typ)



Standby: 3

µW

(typ)

•

Completely static memory. No clock or timing strobe required

•

Equal access and cycle times

•

Common data input and output: Three state output

•

Directly LV-TTL compatible: All inputs

•

Battery backup operation

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