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EP1S30F484I5

Description
Field Programmable Gate Array, CMOS, PBGA484, 23 X 23 MM, 1 MM PITCH, FBGA-484
CategoryProgrammable logic devices    Programmable logic   
File Size3MB,276 Pages
ManufacturerIntel
Websitehttp://www.intel.com/
Download Datasheet Parametric View All

EP1S30F484I5 Overview

Field Programmable Gate Array, CMOS, PBGA484, 23 X 23 MM, 1 MM PITCH, FBGA-484

EP1S30F484I5 Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
package instructionBGA,
Reach Compliance Codecompliant
JESD-30 codeS-PBGA-B484
JESD-609 codee0
Number of terminals484
Package body materialPLASTIC/EPOXY
encapsulated codeBGA
Package shapeSQUARE
Package formGRID ARRAY
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Programmable logic typeFIELD PROGRAMMABLE GATE ARRAY
Certification statusNot Qualified
Maximum supply voltage1.575 V
Minimum supply voltage1.425 V
Nominal supply voltage1.5 V
surface mountYES
technologyCMOS
Terminal surfaceTIN LEAD
Terminal formBALL
Terminal locationBOTTOM
Maximum time at peak reflow temperatureNOT SPECIFIED
Base Number Matches1
Section I. Stratix Device
Family Data Sheet
This section provides the data sheet specifications for Stratix
®
devices.
They contain feature definitions of the internal architecture,
configuration and JTAG boundary-scan testing information, DC
operating conditions, AC timing parameters, a reference to power
consumption, and ordering information for Stratix devices.
This section contains the following chapters:
Chapter 1, Introduction
Chapter 2, Stratix Architecture
Chapter 3, Configuration & Testing
Chapter 4, DC & Switching Characteristics
Chapter 5, Reference & Ordering Information
Revision History
Chapter
1
The table below shows the revision history for
Chapters 1
through
5.
Date/Version
July 2005, v3.2
September 2004, v3.1
April 2004, v3.0
Changes Made
Minor content changes.
Updated
Table 1–6 on page 1–5.
Main section page numbers changed on first page.
Changed PCI-X to PCI-X 1.0 in
“Features” on page 1–2.
Global change from SignalTap to SignalTap II.
The DSP blocks in
“Features” on page 1–2
provide dedicated
implementation of multipliers that are now “faster than 300 MHz.”
Updated -5 speed grade device information in Table 1-6.
Add -8 speed grade device information.
Format changes throughout chapter.
January 2004, v2.2
October 2003, v2.1
July 2003, v2.0
Altera Corporation
Section I–1
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