Field Programmable Gate Array, 612 CLBs, 250000 Gates, 572MHz, 5508-Cell, CMOS, PQFP144, 22 X 22 MM, 1.60 MM HEIGHT, 0.50 MM PITCH, LEAD FREE, TQFP-144
Field Programmable Gate Array, 612 CLBs, 250000 Gates, 572MHz, 5508-Cell, CMOS, PQFP144, 22 X 22 MM, 1.60 MM HEIGHT, 0.50 MM PITCH, LEAD FREE, TQFP-144
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8
Spartan-3E FPGA Family:
Introduction and Ordering Information
Product Specification
DS312 (v4.2) December 14, 2018
Introduction
The Spartan®-3E family of Field-Programmable Gate
Arrays (FPGAs) is specifically designed to meet the needs
of high volume, cost-sensitive consumer electronic
applications. The five-member family offers densities
ranging from 100,000 to 1.6 million system gates, as shown
in
Table 1.
The Spartan-3E family builds on the success of the earlier
Spartan-3 family by increasing the amount of logic per I/O,
significantly reducing the cost per logic cell. New features
improve system performance and reduce the cost of
configuration. These Spartan-3E FPGA enhancements,
combined with advanced 90 nm process technology, deliver
more functionality and bandwidth per dollar than was
previously possible, setting new standards in the
programmable logic industry.
Because of their exceptionally low cost, Spartan-3E FPGAs
are ideally suited to a wide range of consumer electronics
applications, including broadband access, home
networking, display/projection, and digital television
equipment.
The Spartan-3E family is a superior alternative to mask
programmed ASICs. FPGAs avoid the high initial cost, the
lengthy development cycles, and the inherent inflexibility of
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Spartan-3E FPGA Family: Introduction and Ordering Information
Architectural Overview
The Spartan-3E family architecture consists of five
fundamental programmable functional elements:
•
Configurable Logic Blocks (CLBs)
contain flexible
Look-Up Tables (LUTs) that implement logic plus
storage elements used as flip-flops or latches. CLBs
perform a wide variety of logical functions as well as
store data.
Input/Output Blocks (IOBs)
control the flow of data
between the I/O pins and the internal logic of the
device. Each IOB supports bidirectional data flow plus
3-state operation. Supports a variety of signal
standards, including four high-performance differential
standards. Double Data-Rate (DDR) registers are
included.
Block RAM
provides data storage in the form of
18-Kbit dual-port blocks.
Multiplier Blocks
accept two 18-bit binary numbers as
inputs and calculate the product.
•
Digital Clock Manager (DCM) Blocks
provide
self-calibrating, fully digital solutions for distributing,
delaying, multiplying, dividing, and phase-shifting clock
signals.
•
These elements are organized as shown in
Figure 1.
A ring
of IOBs surrounds a regular array of CLBs. Each device has
two columns of block RAM except for the XC3S100E, which
has one column. Each RAM column consists of several
18-Kbit RAM blocks. Each block RAM is associated with a
dedicated multiplier. The DCMs are positioned in the center
with two at the top and two at the bottom of the device. The
XC3S100E has only one DCM at the top and bottom, while
the XC3S1200E and XC3S1600E add two DCMs in the
middle of the left and right sides.
The Spartan-3E family features a rich network of traces that
interconnect all five functional elements, transmitting
signals among them. Each functional element has an
associated switch matrix that permits multiple connections
to the routing.
•
•
X-Ref Target - Figure 1
Figure 1:
Spartan-3E Family Architecture
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Spartan-3E FPGA Family: Introduction and Ordering Information
Configuration
Spartan-3E FPGAs are programmed by loading
configuration data into robust, reprogrammable, static
CMOS configuration latches (CCLs) that collectively control
all functional elements and routing resources. The FPGA’s
configuration data is stored externally in a PROM or some
other non-volatile medium, either on or off the board. After
applying power, the configuration data is written to the
FPGA using any of seven different modes:
•
•
•
•
•
•
Master Serial from a Xilinx Platform Flash PROM
Serial Peripheral Interface (SPI) from an
industry-standard SPI serial Flash
Byte Peripheral Interface (BPI) Up or Down from an
industry-standard x8 or x8/x16 parallel NOR Flash
Slave Serial, typically downloaded from a processor
Slave Parallel, typically downloaded from a processor
Boundary Scan (JTAG), typically downloaded from a
processor or system tester.
I/O Capabilities
The Spartan-3E FPGA SelectIO interface supports many
popular single-ended and differential standards.
Table 2
shows the number of user I/Os as well as the number of
differential I/O pairs available for each device/package
combination.
Spartan-3E FPGAs support the following single-ended
standards:
•
•
•
•
•
3.3V low-voltage TTL (LVTTL)
Low-voltage CMOS (LVCMOS) at 3.3V, 2.5V, 1.8V,
1.5V, or 1.2V
3V PCI at 33 MHz, and in some devices,
66 MHz
HSTL I and III at 1.8V, commonly used in memory
applications
SSTL I at 1.8V and 2.5V, commonly used for memory
applications
Spartan-3E FPGAs support the following differential
standards:
•
•
•
•
•
•
•
LVDS
Bus LVDS
mini-LVDS
RSDS
Differential HSTL (1.8V, Types I and III)
Differential SSTL (2.5V and 1.8V, Type I)
2.5V LVPECL inputs
Furthermore, Spartan-3E FPGAs support MultiBoot
configuration, allowing two or more FPGA configuration
bitstreams to be stored in a single parallel NOR Flash. The
FPGA application controls which configuration to load next
and when to load it.
Table 2:
Available User I/Os and Differential (Diff) I/O Pairs
Package
Footprint
Size (mm)
Device
XC3S100E
XC3S250E
XC3S500E
XC3S1200E
XC3S1600E
Notes:
1.
2.
3.
All Spartan-3E devices provided in the same package are pin-compatible as further described in Module 4,
Pinout Descriptions.
The number shown in
bold
indicates the maximum number of I/O and input-only pins. The number shown in (italics) indicates the number
of input-only pins.
The XC3S500E is available in the VQG100 Pb-free package and not the standard VQ100. The VQG100 and VQ100 pin-outs are identical
and general references to the VQ100 will apply to the XC3S500E.
VQ100
VQG100
16 x 16
User
66
(2)
9(7)
66
(7)
66
(3)
(7)
-
-
Diff
30
(2)
30
(2)
30
(2)
-
-
CP132
CPG132
8x8
User
83
(11)
92
(7)
92
(7)
-
-
Diff
35
(2)
41
(2)
41
(2)
-
-
TQ144
TQG144
22 x 22
User
108
(28)
108
(28)
-
-
-
Diff
40
(4)
40
(4)
-
-
-
PQ208
PQG208
30.5 x 30.5
User
-
158
(32)
158
(32)
-
-
Diff
-
65
(5)
65
(5)
-
-
FT256
FTG256
17 x 17
User
-
172
(40)
190
(41)
190
(40)
-
Diff
-
68
(8)
77
(8)
77
(8)
-
FG320
FGG320
19 x 19
User
-
-
232
(56)
250
(56)
250
(56)
Diff
-
-
92
(12)
99
(12)
99
(12)
FG400
FGG400
21 x 21
User
-
-
-
304
(72)
304
(72)
Diff
-
-
-
124
(20)
124
(20)
FG484
FGG484
23 x 23
User
-
-
-
-
376
(82)
Diff
-
-
-
-
156
(21)
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Spartan-3E FPGA Family: Introduction and Ordering Information
Package Marking
Figure 2
provides a top marking example for Spartan-3E
FPGAs in the quad-flat packages.
Figure 3
shows the top
marking for Spartan-3E FPGAs in BGA packages except
the 132-ball chip-scale package (CP132 and CPG132). The
markings for the BGA packages are nearly identical to those
for the quad-flat packages, except that the marking is
rotated with respect to the ball A1 indicator.
Figure 4
shows
the top marking for Spartan-3E FPGAs in the CP132 and
CPG132 packages.
X-Ref Target - Figure 2
On the QFP and BGA packages, the optional numerical
Stepping Code follows the Lot Code.
The “5C” and “4I” part combinations can have a dual mark
of “5C/4I”. Devices with a single mark are only guaranteed
for the marked speed grade and temperature range. All “5C”
and “4I” part combinations use the Stepping 1 production
silicon.
Mask Revision Code
Fabrication Code
R
SPARTAN
Device Type
Package
Speed Grade
Temperature Range
TM
R
Process Technology
Date Code
Stepping Code
(optional)
Lot Code
XC3S250E
PQ208AGQ0525
D1234567A
4C
Pin P1
DS312-1_06_102905
Figure 2:
Spartan-3E QFP Package Marking Example
X-Ref Target - Figure 3
Mask Revision Code
BGA Ball A1
Device Type
Package
R
SPARTAN
R
Fabrication Code
Process Code
XC3S250E
TM
FT256AGQ0525
D1234567A
4C
Date Code
Stepping Code
(optional)
Lot Code
Speed Grade
Temperature Range
DS312-1_02_090105
Figure 3:
Spartan-3E BGA Package Marking Example
X-Ref Target - Figure 4
Ball A1
Lot Code
3S250E
F1234567-0525
PHILIPPINES
Device Type
Date Code
Temperature Range
Package
C5 = CP132
C6 = CPG132
C5AGQ
4C
Speed Grade
Process Code
Fabrication Code
DS312-1_05_032105
Mask Revision Code
Figure 4:
Spartan-3E CP132 and CPG132 Package Marking Example
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