April 2002
Preliminary
®
AS7C33512PFS16A
AS7C33512PFS18A
3.3V 512K
×
16/18 pipeline burst synchronous SRAM
Features
•
•
•
•
•
•
•
Organization: 524,288 words × 16 or 18 bits
Fast clock speeds to 166 MHz in LVTTL/LVCMOS
Fast clock to data access: 3.5/3.8/4.0/5.0 ns
Fast OE access time: 3.5/3.8/4.0/5.0 ns
Fully synchronous register-to-register operation
Single register “Flow-through” option
Single-cycle deselect
- Dual-cycle deselect also available (AS7C33512PFD16A/
AS7C33512PFD18A)
• Available in both 2 chip enable and 3 chip enable
- 2 CE part number is AS7C33512PFS16A or AS7C33512PFS18A2
• Asynchronous output enable control
• Available in 100-pin TQFP and 119-ball BGA package
• Byte write enables
• Multiple chip enables for easy expansion
• 3.3V core power supply
• 2.5V or 3.3V I/O operation with separate V
DDQ
• 30 mW typical standby power in power down mode
• NTD™
1
pipeline architecture available
(AS7C33512NTD16A/AS7C33512NTD18A)
1. Pentium
®
is a registered trademark of Intel Corporation. NTD™ is a
trademark of Alliance Semiconductor Corporation. All trademarks men-
tioned in this document are the property of their respective owners.
• Pentium®
1
compatible architecture and timing
Logic block diagram
LBO
CLK
ADV
ADSC
ADSP
A[18:0]
CLK
CS
CLR
Burst logic
Q
19
D
CS
CLK
19
17 19
Address
register
512K × 16/18
Memory
array
16/18 16/18
GWE
BW
b
BWE
BW
a
CE0
CE1
CE2
D
DQb
Q
Byte Write
registers
Byte Write
registers
CLK
D
CLK
D
DQa
Q
2
OE
Enable
Q
register
CE
CLK
ZZ
Output
registers
CLK
Input
registers
CLK
Power
down
D
Enable
Q
delay
register
CLK
OE
16/18
FT
DQ[a,b]
Selection guide
–166
Minimum cycle time
Maximum pipelined clock frequency
Maximum pipelined clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
6
166
3.5
475
130
30
–150
6.6
150
3.8
450
110
30
–133
7.5
133
4
425
100
30
–100
10
100
5
325
90
30
Units
ns
MHz
ns
mA
mA
mA
4/15/02;
v.1.5
Alliance Semiconductor
1 of 14
Copyright © Alliance Semiconductor. All rights reserved.
AS7C33512PFS16A
AS7C33512PFS18A
®
Pin arrangement for 3 chip enable
A6
A7
CE0
CE1
NC
NC
BWb
BWa
CE2
V
DD
V
SS
CLK
GWE
BWE
OE
ADSC
ADSP
ADV
A8
A9
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
NC
NC
NC
V
DDQ
V
SSQ
NC
NC
DQb
DQb
V
SSQ
V
DDQ
DQb
DQb
FT
V
DD
NC
V
SS
DQb
DQb
V
DDQ
V
SSQ
DQb
DQb
DQpb/NC
NC
V
SSQ
V
DDQ
NC
NC
NC
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A6
A7
CE0
CE1
NC
NC
BWb
BWa
A 18
V
DD
V
SS
CLK
GWE
BWE
OE
ADSC
ADSP
ADV
A8
A9
Pin arrangement for 2chip enable
LBO
A5
A4
A3
A2
A1
A0
NC
NC
V
SS
V
DD
NC
A18
A10
A11
A12
A13
A14
A15
A16
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
TQFP 14 × 20mm
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A17
NC
NC
V
DDQ
V
SSQ
NC
DQpa/NC
DQa
DQa
V
SSQ
V
DDQ
DQa
DQa
VSS
NC
V
DD
ZZ
DQa
DQa
V
DDQ
V
SSQ
DQa
DQa
NC
NC
V
SSQ
V
DDQ
NC
NC
NC
Note: pins 24, 74 are NC for ×16.
NC
NC
NC
V
DDQ
V
SSQ
NC
NC
DQb
DQb
V
SSQ
V
DDQ
DQb
DQb
FT
V
DD
NC
V
SS
DQb
DQb
V
DDQ
V
SSQ
DQb
DQb
DQpb/NC
NC
V
SSQ
V
DDQ
NC
NC
NC
4/15/02; v.1.5
Alliance Semiconductor
LBO
A5
A4
A3
A2
A1
A0
NC
NC
V
SS
V
DD
NC
NC
A10
A11
A12
A13
A14
A15
A16
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
TQFP 14 × 20mm
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A17
NC
NC
V
DDQ
V
SSQ
NC
DQpa/NC
DQa
DQa
V
SSQ
V
DDQ
DQa
DQa
VSS
NC
V
DD
ZZ
DQa
DQa
V
DDQ
V
SSQ
DQa
DQa
NC
NC
V
SSQ
V
DDQ
NC
NC
NC
Note: pins 24, 74 are NC for ×16.
2 of 14
AS7C33512PFS16A
AS7C33512PFS18A
®
Pin Configuration for 512 x 18
1
for 119-ball BGA
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC
NC
DQ
b
NC
V
DDQ
NC
DQ
b
V
DDQ
NC
DQb
V
DDQ
DQb
NC
NC
NC
V
DDQ
2
A
CE2
A
NC
DQb
NC
DQb
NC
V
DD
DQb
NC
DQb
NC
DQPb
A
A
NC
3
A
A
A
V
SS
V
SS
V
SS
BWb
V
SS
NC
V
SS
V
SS
V
SS
V
SS
V
SS
LBO
A
NC
4
ADSP
ADSC
V
DD
NC
CE1
OE
ADV
GWE
V
DD
CLK
NC
BWE
A1
2
A0
2
V
DD
NC
NC
5
A
A
A
V
SS
V
SS
V
SS
V
SS
V
SS
NC
V
SS
BWa
V
SS
V
SS
V
SS
FT
A
NC
6
A
A
A
DQPa
NC
DQa
NC
DQa
V
DD
NC
DQa
NC
DQa
NC
A
A
NC
7
V
DDQ
NC
NC
NC
DQa
V
DDQ
DQa
NC
V
DDQ
DQa
NC
V
DDQ
NC
DQa
NC
ZZ
V
DDQ
1 Note pins 6D and 2P are NC for x16.
2 A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst
counter if burst is desired.
4/15/02; v.1.5
Alliance Semiconductor
3 of 14
AS7C33512PFS16A
AS7C33512PFS18A
®
Functional description
The AS7C33512PFS16A and AS7C33512PFS18A are high performance CMOS 8-Mbit synchronous Static Random Access Memory (SRAM)
devices organized as 524,288 words × 16 or 18 bits and incorporate a pipeline for highest frequency on any given technology.
Timing for this device is compatible with existing Pentium
®
synchronous cache specifications. This architecture is suited for ASIC, DSP
(TMS320C6X), and PowerPC
™
-based systems in computing, datacom, instrumentation, and telecommunications systems.
Fast cycle times of 6/6.6/7.5/10 ns with clock access times (t
CD
) of 3.5/3.8/4.0/5.0 ns enable 166, 150, 133 and 100 MHz bus frequencies.
Three chip enable inputs permit easy memory expansion. Burst operation is initiated in one of two ways: the controller address strobe (ADSC),
or the processor address strobe (ADSP). The burst advance pin (ADV) allows subsequent internally generated burst addresses.
Read cycles are initiated with ADSP (regardless of WE and ADSC) using the new external address clocked into the on-chip address register.
When ADSP is sampled LOW, the chip enables are sampled active, and the output buffer is enabled with OE. In a read operation the data
accessed by the current address, registered in the address registers by the positive edge of CLK, are carried to the data-out registers and driven
on the output pins on the next positive edge of CLK. ADV is ignored on the clock edge that samples ADSP asserted but is sampled on all
subsequent clock edges. Address is incremented internally for the next access of the burst when ADV is sampled LOW and both address strobes
are HIGH. Burst mode is selectable with the LBO input. With LBO unconnected or driven HIGH, burst operations use a Pentium
®1
count
sequence. With LBO driven LOW the device uses a linear count sequence suitable for PowerPC
™
and many other applications.
Write cycles are performed by disabling the output buffers with OE and asserting a write command. A global write enable GWE writes all 16/
18 bits regardless of the state of individual BW[a:b] inputs. Alternately, when GWE is HIGH, one or more bytes may be written by asserting
BWE and the appropriate individual byte BWn signal(s).
BWn is ignored on the clock edge that samples ADSP LOW, but is sampled on all subsequent clock edges. Output buffers are disabled when
BWn is sampled LOW (regardless of OE). Data is clocked into the data input register when BWn is sampled LOW. Address is incremented
internally to the next burst address if BWn and ADV are sampled LOW.
Read or write cycles may also be initiated with ADSC instead of ADSP. The differences between cycles initiated with ADSC and ADSP follow.
• ADSP must be sampled HIGH when ADSC is sampled LOW to initiate a cycle with ADSC.
• WE signals are sampled on the clock edge that samples ADSC LOW (and ADSP HIGH).
• Master chip select CE0 blocks ADSP, but not ADSC.
The AS7C33512PFS16A and AS7C33512PFS18A operate from a 3.3V supply. I/Os use a separate power supply that can operate at 2.5V or 3.3V.
These devices are available in a 100-pin 14×20 mm TQFP and 119-ball BGA packaging.
Capacitance
Parameter
Input capacitance
I/O capacitance
Symbol
C
IN
C
I/O
Signals
Address and control pins
I/O pins
Test conditions
V
IN
= 0V
V
IN
= V
OUT
= 0V
Max
5
7
Unit
pF
pF
Write enable truth table (per byte)
GWE
L
H
H
H
BWE
X
L
H
L
BWn
X
L
X
H
WEn
T
T
F*
F*
Key: X = Don’t Care, L = Low, H = High, T=True, F=False; * valid read; n = a,b;
WE, WEn
= internal write signal
Burst Order
Interleaved Burst Order
Starting Address
First increment
Second increment
Third increment
00
01
10
11
LBO=1
01
10
00
11
11
00
10
01
11
10
01
00
Starting Address
First increment
Second increment
Third increment
Linear Burst Order
00
01
10
11
LBO=0
01
10
10
11
11
00
00
01
11
00
01
10
1. PowerPC
™
is a trademark International Business Machines Corporation
4/15/02; v.1.5
Alliance Semiconductor
4 of 14
AS7C33512PFS16A
AS7C33512PFS18A
®
Signal descriptions
Signal
CLK
A0–A18
DQ[a,b]
CE0
CE1, CE2
ADSP
ADSC
ADV
GWE
BWE
BW[a,b]
OE
LBO
I/O
I
I
I/O
I
I
I
I
I
I
I
I
I
I
I
I
Properties
CLOCK
SYNC
SYNC
SYNC
SYNC
SYNC
SYNC
SYNC
SYNC
SYNC
SYNC
ASYNC
STATIC
STATIC
ASYNC
Description
Clock. All inputs except OE,
FT
, ZZ,
LBO
are synchronous to this clock.
Address. Sampled when all chip enables are active and ADSC or ADSP are asserted.
Data. Driven as output when the chip is enabled and OE is active.
Master chip enable. Sampled on clock edges when ADSP or ADSC is active. When
CE0 is inactive, ADSP is blocked. Refer to the Synchronous Truth Table for more
information.
Synchronous chip enables. Active HIGH and active LOW, respectively. Sampled on
clock edges when ADSC is active or when CE0 and ADSP are active.
Address strobe (processor). Asserted LOW to load a new address or to enter standby
mode.
Address strobe (controller). Asserted LOW to load a new address or to enter standby
mode.
Burst advance. Asserted LOW to continue burst read/write.
Global write enable. Asserted LOW to write all 16/18 bits. When HIGH, BWE and
BW[a,b] control write enable.
Byte write enable. Asserted LOW with GWE = HIGH to enable effect of BW[a,b]
inputs.
Write enables. Used to control write of individual bytes when GWE = HIGH and
BWE = LOW. If any of BW[a,b] is active with GWE = HIGH and BWE = LOW the
cycle is a write cycle. If all BW[a,b] are inactive, the cycle is a read cycle.
Asynchronous output enable. I/O pins are driven when OE is active and the chip is
in read mode.
Count mode. When driven HIGH, count sequence follows Intel XOR convention.
When driven LOW, count sequence follows linear convention. This signal is
internally pulled HIGH.
Flow-through mode.When LOW, enables single register flow-through mode.
Connect to V
DD
if unused or for pipelined operation.
Snooze. Places device in low power mode; data is retained. Connect to GND if
unused.
FT
ZZ
Absolute maximum ratings
Parameter
Power supply voltage relative to GND
Input voltage relative to GND (input pins)
Input voltage relative to GND (I/O pins)
Power dissipation
DC output current
Storage temperature (plastic)
Temperature under bias
Symbol
V
DD
, V
DDQ
V
IN
V
IN
P
D
I
OUT
T
stg
T
bias
Min
–0.5
–0.5
–0.5
–
–
–65
–65
Max
+4.6
V
DD
+ 0.5
V
DDQ
+ 0.5
1.8
50
+150
+135
Unit
V
V
V
W
mA
°
C
°
C
Note: Stresses greater than those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress rating only and functional opera-
tion of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions may affect reliability.
4/15/02; v.1.5
Alliance Semiconductor
5 of 14
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