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MITSUBISHI MICROCOMPUTERS
M37733M4BXXXFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DESCRIPTION
The M37733M4BXXXFP is a single-chip microcomputer using the
7700 Family core. This single-chip microcomputer has a CPU and a
bus interface unit. The CPU is a 16-bit parallel processor that can be
an 8-bit parallel processor, and the bus interface unit enhances the
memory access efficiency to execute instructions fast. This
microcomputer also includes a 32 kHz oscillation circuit, in addition
to the ROM, RAM, multiple-function timers, serial I/O, A-D converter,
and so on.
qSerial
I/O (UART or clock synchronous) ..................................... 3
q10-bit
A-D converter ............................................ 8-channel inputs
q12-bit
watchdog timer
qProgrammable
input/output
(ports P0, P1, P2, P3, P4, P5, P6, P7, P8) ............................... 68
qClock
generating circuit ........................................ 2 circuits built-in
APPLICATION
Control devices for general commercial equipment such as office
automation, office equipment, and so on.
Control devices for general industrial equipment such as
communication equipment, and so on.
FEATURES
qNumber
of basic instructions .................................................. 103
qMemory
size
ROM ................................................. 32 Kbytes
RAM ................................................ 2048 bytes
qInstruction
execution time
The fastest instruction at 25 MHz frequency ...................... 160 ns
qSingle
power supply ...................................................... 5 V ± 10%
qLow
power dissipation (at 25 MHz frequency)
............................................47.5 mW (Typ.)
qInterrupts
............................................................ 19 types, 7 levels
qMultiple-function
16-bit timer ................................................. 5 + 3
PIN CONFIGURATION (TOP VIEW)
P8
4
/
CTS
1
/
RTS
1
P8
5
/CLK
1
P8
6
/R
X
D
1
P8
7
/T
X
D
1
P0
0
/
A
0
P0
1
/
A
1
P0
2
/
A
2
P0
3
/
A
3
P0
4
/
A
4
P0
5
/
A
5
P0
6
/A
6
P0
7
/A
7
P1
0
/A
8
/D
8
P1
1
/A
9
/D
9
P1
2
/A
10
/D
10
P1
3
/A
11
/D
11
P1
4
/A
12
/D
12
P1
5
/A
13
/D
13
P1
6
/A
14
/D
14
P1
7
/A
15
/D
15
P2
0
/A
16
/D
0
P2
1
/A
17
/D
1
P2
2
/A
18
/D
2
P2
3
/A
19
/D
3
64
62
59
53
60
57
61
58
49
48
47
46
42
56
50
54
63
52
P8
3
/T
X
D
0
P8
2
/R
X
D
0
/CLKS
0
P8
1
/CLK
0
P8
0
/CTS
0
/RTS
0
/
CLKS
1
V
CC
AV
CC
V
REF
AV
SS
V
SS
P7
7
/AN
7
/Xc
IN
P7
6
/AN
6
/Xc
OUT
P7
5
/AN
5
/
AD
TRG
/TxD
2
P7
4
/AN
4
/RxD
2
P7
3
/AN
3
/CLK
2
P7
2
/AN
2
/CTS
2
P7
1
/AN
1
55
51
45
44
43
41
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
21
10
11
12
15
16
14
17
18
20
13
19
22
23
24
40
39
38
37
36
35
34
M37733M4BXXXFP
33
32
31
30
29
28
27
26
25
P2
4
/A
20
/D
4
P2
5
/A
21
/D
5
P2
6
/A
22
/D
6
P2
7
/A
23
/D
7
P3
0
/
R/W
P3
1
/
BHE
P3
2
/
ALE
P3
3
/
HLDA
V
ss
E
X
OUT
X
IN
RESET
CNV
SS
BYTE
P4
0
/
HOLD
3
4
1
2
P7
0
/AN
0
P6
7
/TB2
IN
/φ
SUB
P6
6
/TB1
IN
P6
5
/TB0
IN
P6
4
/I
NT
2
P6
3
/I
NT
1
P6
2
/I
NT
0
P6
1
/TA4
IN
P6
0
/TA4
OUT
P5
7
/TA3
IN
/
KI
3
P5
6
/TA3
OUT
/
KI
2
P5
5
/TA2
IN
/
KI
1
P5
4
/TA2
OUT
/
KI
0
P5
3
/TA1
IN
P5
2
/TA1
OUT
P5
1
/TA0
IN
P5
0
/TA0
OUT
P4
7
P4
6
P4
5
P4
4
P4
3
P4
2
/φ
1
P4
1
/
RDY
5
6
7
8
9
Outline 80P6N-A
1
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M
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MITSUBISHI MICROCOMPUTERS
M37733M4BXXXFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
External data bus width
Reference
voltage input
selection input
V
REF
BYTE
Data Bus(Even)
Data Bus(Odd)
Data Buffer DB
H
(8)
P0(8)
Data Buffer DB
L
(8)
Instruction Register(8)
Instruction Queue Buffer Q
0
(8)
Instruction Queue Buffer Q
1
(8)
Address Bus
Incrementer(24)
(0V)
AV
SS
Program Address Register PA(24)
Data Address Register DA(24)
Input/Output
port P2
Input/Output
port P8
Input/Output
port P7
Input/Output
port P6
Input/Output
port P5
Input/Output
port P4
Input/Output
port P3
P2(8)
CNVss
Incrementer/Decrementer(24)
(0V)
V
SS
Program Bank Register PG(8)
Data Bank Register DT(8)
UART2(9)
UART1(9)
UART0(9)
V
CC
Input Butter Register IB(16)
Watchdog Timer
Timer TB2(16)
Timer TB1(16)
Timer TB0(16)
Processor Status Register PS(11)
Reset input
RESET
Direct Page Register DPR(16)
Stack Pointer S(16)
Timer TA4(16)
Timer TA3(16)
M37733M4BXXXFP BLOCK DIAGRAM
Timer TA2(16)
Timer TA1(16)
Timer TA0(16)
Index Register Y(16)
X
COUT
X
CIN
Index Register X(16)
Accumulator B(16)
Enable output
E
Accumulator A(16)
Clock Generating Circuit
2048 bytes
P7(8)
Clock input Clock output
X
IN
X
OUT
RAM
Arithmetic Logic
Unit(16)
X
COUT
X
CIN
32 Kbytes
2
ROM
P8(8)
P6(8)
P5(8)
P4(8)
P3(4)
Program Counter PC(16)
A-D Converter(10)
Input/Output
port P1
Instruction Queue Buffer Q
2
(8)
P1(8)
AV
CC
Input/Output
port P0
PR
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Not e para
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M
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MITSUBISHI MICROCOMPUTERS
M37733M4BXXXFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
FUNCTIONS OF M37733M4BXXXFP
Parameter
Number of basic instructions
Instruction execution time
Memory size
Input/Output ports
Multi-function timers
Serial I/O
A-D converter
Watchdog timer
Interrupts
Clock generating circuit
Supply voltage
Power dissipation
Input/Output characteristic
Memory expansion
Operating temperature range
Device structure
Package
Input/Output voltage
Output current
ROM
RAM
P0 – P2, P4 – P8
P3
TA0, TA1, TA2, TA3, TA4
TB0, TB1, TB2
Functions
103
160 ns (the fastest instruction at external clock 25 MHz frequency)
32 Kbytes
2048 bytes
8-bit
!
8
4-bit
!
1
16-bit
!
5
16-bit
!
3
(UART or clock synchronous serial I/O)
!
3
10-bit
!
1 (8 channels)
12-bit
!
1
3 external types, 16 internal types
Each interrupt can be set to the priority level (0 – 7.)
2 circuits built-in (externally connected to a ceramic resonator or a
quartz-crystal oscillator)
5 V ± 10%
47.5 mW (at external clock 25 MHz frequency)
5V
5 mA
Maximum 16 Mbytes
–20 to 85 °C
CMOS high-performance silicon gate process
80-pin plastic molded QFP (80P6N-A)
3
PRE
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tion hange
c
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pec ject to
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fina re sub
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c
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ic
Not e par
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MITSUBISHI MICROCOMPUTERS
M37733M4BXXXFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
PIN DESCRIPTION
Pin
Vcc,
Vss
CNVss
_____
Name
Input/Output
Power source
Apply 5 V ± 10% to Vcc and 0 V to Vss.
CNVss input
Reset input
Clock input
Clock output
Enable output
External data
bus width
selection input
Analog power
source input
Reference
voltage input
I/O port P0
Input
Input
Input
Output
Output
Input
Functions
RESET
X
IN
_
X
OUT
E
BYTE
AVcc,
AVss
V
REF
P0
0
– P0
7
This pin controls the processor mode. Connect to Vss for the single-chip mode and the memory
expansion mode, and to Vcc for the microprocessor mode.
When “L” level is applied to this pin, the microcomputer enters the reset state.
These are pins of main-clock generating circuit. Connect a ceramic resonator or a quartz-
crystal oscillator between X
IN
and X
OUT
. When an external clock is used, the clock source should
be connected to the X
IN
pin, and the X
OUT
pin should be left open.
This pin functions as the enable signal output pin which indicates the access status in the internal
_
bus. When output level of
E
signal is “L”, data/instruction read or data write is performed.
In the memory expansion mode or the microprocessor mode, this pin determines whether the
external data bus has an 8-bit width or a 16-bit width. The data bus has a 16-bit width when “L”
signal is input and an 8-bit width when “H” signal is input.
Power source input pin for the A-D converter. Externally connect AVcc to Vcc and AVss to Vss.
This is reference voltage input pin for the A-D converter.
In the single-chip mode, port P0 becomes an 8-bit I/O port. An I/O direction register is available so
that each pin can be programmed for input or output. These ports are in the input mode when
reset.
In the memory expansion mode or the microprocessor mode, these pins output address (A
0
– A
7
).
In the single-chip mode, these pins have the same functions as port P0. When the BYTE pin is set
to “L” in the memory expansion mode or the microprocessor mode and external data bus has a
16-bit width, high-order data (D
8
– D
15
) is input/output or an address (A
8
– A
15
) is output. When
the BYTE pin is “H” and an external data bus has an 8-bit width, only address (A
8
– A
15
) is output.
In the single-chip mode, these pins have the same functions as port P0. In the memory expansion
mode or the microprocessor mode, low-order data (D
0
– D
7
) is input/output or an address
(A
0
– A
7
) is output .
In the single-chip mode, these pins have the same function as port P0. In the memory expansion
____
__ ___
mode or the microprocessor mode, R/
W
,
BHE
, ALE, and
HLDA
signals are output.
In the single-chip mode, these pins have the same functions as port P0. In the memory expansion
____
___
mode or the microprocessor mode, P4
0
, P4
1
and P4
2
become
HOLD
and
RDY
input pins, and a
clock
φ
1
output pin, respectively. Functions of the other pins are the same as in the single-chip
mode. However, in the memory expansion mode, P4
2
can be selected as an I/O port.
In addition to having the same functions as port P0 in the single-chip mode, these pins also
__
__
function as I/O pins for timers A0 to A3 and input pins for key input interrupt input (
KI
0
–
KI
3
).
In addition to having the same functions as port P0 in the single-chip mode, these pins also
___
___
function as I/O pins for timer A4, input pins for external interrupt input (
INT
0
–
INT
2
) and input pins
for timers B0 to B2. P6
7
also functions as sub-clock
φ
SUB
output pin.
In addition to having the same functions as port P0 in the single-chip mode, these pins function as
input pins for A-D converter. P7
2
to P7
5
also function as I/O pins for UART2. Additionally, P7
6
and
P7
7
have the function as the output pin (X
COUT
) and the input pin (X
CIN
) of the sub-clock (32 kHz)
oscillation circuit, respectively. When P7
6
and P7
7
are used as the X
COUT
and X
CIN
pins, connect
a resonator or an oscillator between the both.
In addition to having the same functions as port P0 in the single-chip mode, these pins also
function as I/O pins for UART 0 and UART 1.
Input
I/O
P1
0
– P1
7
I/O port P1
I/O
P2
0
– P2
7
I/O port P2
I/O
P3
0
– P3
3
I/O port P3
P4
0
– P4
7
I/O port P4
I/O
I/O
P5
0
– P5
7
I/O port P5
P6
0
– P6
7
I/O port P6
I/O
I/O
P7
0
– P7
7
I/O port P7
I/O
P8
0
– P8
7
I/O port P8
I/O
4
PRE
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c
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MITSUBISHI MICROCOMPUTERS
M37733M4BXXXFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
BASIC FUNCTION BLOCKS
The M37733M4BXXXFP has the same functions as the
M37733MHBXXXFP except for the memory allocation and the ROM
area modification function.
Refer to the section on the M37733MHBXXXFP.
MEMORY
The memory map is shown in Figure 1. The address space has a
capacity of 16 Mbytes and is allocated to addresses from 0
16
to
FFFFFF
16
. The address space is divided by 64-Kbyte unit called bank.
The banks are numbered from 0
16
to FF
16
.
Built-in ROM, RAM and control registers for internal peripheral devices
are assigned to bank 0
16
.
The 32-Kbyte area from addresses 8000
16
to FFFF
16
is the built-in
ROM. Addresses FFD6
16
to FFFF
16
are the RESET and interrupt
vector addresses and contain the interrupt vectors. Refer to the section
on interrupts for details.
The 2048-byte area allocated to addresses from 80
16
to 87F
16
is the
built-in RAM. In addition to storing data, the RAM is used as stack
during a subroutine call or interrupts.
Peripheral devices such as I/O ports, A-D converter, serial I/O, timer,
and interrupt control registers are allocated to addresses from 0
16
to
7F
16
.
Additionally, the internal ROM area can be modified by software. Refer
to the section on ROM area modification function for details.
A 256-byte direct page area can be allocated anywhere in bank 0
16
by using the direct page register (DPR). In the direct page addressing
mode, the memory in the direct page area can be accessed with two
words. Hence program steps can be reduced.
000000
16
Bank 0
16
000000
16
00007F
16
000080
16
00087F
16
000000
16
Internal RAM
2048 bytes
Internal peripheral
devices
control registers
refer to Fig. 2 for
detail information
00FFFF
16
010000
16
00007F
16
Bank 1
16
00FFD6
16
01FFFF
16
•••••••••••••••••••
Interrupt vector table
A-D/UART2 trans./rece.
UART1 transmission
UART1 receive
UART0 transmission
UART0 receive
Timer B2
008000
16
Timer B1
Timer B0
Timer A4
Timer A3
Timer A2
FE0000
16
Bank FE
16
FEFFFF
16
FF0000
16
Bank FF
16
00FFD6
16
FFFFFF
16
00FFFF
16
00FFFE
16
Internal ROM
32 Kbytes
Timer A1
Timer A0
INT
2
/Key input
INT
1
INT
0
Watchdog timer
DBC
BRK instruction
Zero divide
RESET
Note.
Internal ROM area can be modified. (Refer to the section on ROM area modification function.)
Fig. 1 Memory map
5
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