HM-6617
March 1997
2K x 8 CMOS PROM
Description
The HM-6617 is a 16,384 bit fuse link CMOS PROM in a 2K
word by 8-bit/word format with “Three-State” outputs. This
PROM is available in the standard 0.600 inch wide 24 pin
SBDIP, the 0.300 inch wide slimline SBDIP, and the JEDEC
standard 32 pad CLCC.
The HM-6617 utilizes a synchronous design technique. This
includes on-chip address latches and a separate output
enable control which makes this device ideal for applications
utilizing recent generation microprocessors. This design
technique, combined with the Intersil advanced self-aligned
silicon gate CMOS process technology offers ultra-low
standby current. Low ICCSB is ideal for battery applications
or other systems with low power requirements.
The Intersil NiCr fuse link technology is utilized on this and
other Intersil CMOS PROMs. This gives the user a PROM
with permanent, stable storage characteristics over the full
industrial and military temperature voltage ranges. NiCr fuse
technology combined with the low power characteristics of
CMOS provides an excellent alternative to standard bipolar
PROMs or NMOS EPROMs.
All bits are manufactured storing a logical “0” and can be
selectively programmed for a logical “1” at any bit location.
Features
• Low Power Standby and Operating Power
- ICCSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100µA
- ICCOP . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA at 1MHz
• Fast Access Time. . . . . . . . . . . . . . . . . . . . . . . 90/120ns
• Industry Standard Pinout
• Single 5.0V Supply
• CMOS/TTL Compatible Inputs
• High Output Drive . . . . . . . . . . . . . . . . 12 LSTTL Loads
• Synchronous Operation
• On-Chip Address Latches
• Separate Output Enable
Ordering Information
PACKAGE TEMP. RANGE
SBDIP
SMD#
SLIM
SBDIP
SMD#
CLCC
SMD#
90ns
6617B-9
-55
o
C to +125
o
C 5962-
120ns
HM1-
6617-9
PKG.
NO.
D24.6
-40
o
C to +85
o
C HM1-
5962-
D24.6
8954002JA 8954001JA
HM6-
6617-9
D24.3
-40
o
C to +85
o
C HM6-
6617B-9
-55
o
C to +125
o
C 5962-
5962-
D24.3
8954002LA 8954001LA
-40
o
C to +85
o
C HM4-
6617B-9
HM4-
6617-9
J32.A
-55
o
C to +125
o
C 5962-
5962-
J32.A
8954002XA 8954001XA
Pinouts
HM-6617 (SBDIP)
TOP VIEW
A7
HM-6617 (CLCC)
TOP VIEW
V
CC
NC
NC
NC
NC
NC
PIN DESCRIPTION
PIN
29 A8
28 A9
27 NC
26 P
25 G
24 A10
23 E
22 Q7
21 Q6
DESCRIPTION
No Connect
Address Inputs
Chip Enable
Data Output
Power (+5V)
Output Enable
Output Enable
A7
A6
A5
A4
A3
A2
A1
A0
Q0
1
2
3
4
5
6
7
8
9
24 V
CC
23 A8
22 A9
21 P
20 G
19 A10
18 E
17 Q7
16 Q6
15 Q5
14 Q4
13 Q3
4
A6 5
A5 6
A4 7
A3 8
A2 9
A1 10
A0 11
NC 12
Q0 13
3
2
1
32 31 30
NC
A0-A10
E
Q
V
CC
G
P (Note)
Q1 10
Q2 11
GND 12
14 15 16 17 18 19 20
Q1
Q2
NC
Q3
Q4
GND
Q5
NOTE: P should be hardwired to V
CC
except during programming.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
©
Intersil Corporation 1999
File Number
3017.1
6-1
HM-6617
Background Information Programming
Algorithm
The HM-6617 CMOS PROM is manufactured with all bits
containing a logical zero (output low). Any bit can be pro-
grammed selectively to a logical one (output high) state by
following the procedure shown below. To accomplish this, a
programmer can be built that meets the specifications
shown, or any of the approved commercial programmers can
be used.
Programming Sequence Of Events
1. Apply a voltage of V
CC1
to V
CC
of the PROM.
2. Read all fuse locations to verify that the PROM is blank
(output low).
3. Place the PROM in the initial state for programming: E =
V
IH
, P = V
IH
, G = V
IL
.
4. Apply the correct binary address for the word to be pro-
grammed. No inputs should be left open circuit.
5. After a delay of tD, apply voltage of V
IL
to E (pin 18) to ac-
cess the addressed word.
6. The address may be held through the cycle, but must be
held valid at least for a time equal to tD after the falling
edge of E. None of the inputs should be allowed to float
to an invalid logic level.
7. After a delay of tD, disable the outputs by applying a volt-
age of V
IH
to G (pin 20).
8. After a delay of tD, apply voltage of V
IL
to P (pin 21).
9. After delay of tD, raise V
CC
(pin 24) to VCCPROG with a
rise time of tR. All outputs at V
IH
should track V
CC
with
V
CC
-2.0V to V
CC
+0.3V. This could be accomplished by
pulling outputs at V
IH
to V
CC
through pull-up resistors of
value Rn.
10. After a delay of tD, pull the output which corresponds to
the bit to be programmed to V
IL
. Only one bit should be
programmed at a time.
11. After a delay of tPW, allow the output to be pulled to V
IH
through pull-up resistor Rn.
12. After a delay of tD, reduce V
CC
(pin 24) to V
CC1
with a fall
time of tF. All outputs at V
IH
should track V
CC
with V
CC
2.0V
to V
CC
+0.3V. This could be accomplished by pulling out-
puts at V
IH
to V
CC
through pull-up resistors of value Rn.
13. Apply a voltage of V
IH
to P (pin 21).
14. After a delay of tD, apply a voltage of V
IL
to G (pin 20).
15. After a delay of tD, examine the outputs for correct data. If
any location verifies incorrectly, repeat steps 4 through 14
(attempting to program only those bits in the word which
verified incorrectly) up to a maximum of eight attempts for
a given word. If a word does not program within eight at-
tempts, it should be considered a programming reject.
16. Repeat steps 3 through 15 for all other bits to be pro-
grammed in the PROM.
Post-Programming Verification
17. Place the PROM in the post-programming verification
mode: E = V
IH
, G = V
IL
, P = V
IH
, V
CC
(pin 24) = V
CC1
.
18. Apply the correct binary address of the word to be veri-
fied to the PROM.
19. After a delay of tD, apply a voltage of V
IL
to E (pin 18).
20. After a delay of tD, examine the outputs for correct data.
If any location fails to verify correctly, the PROM should
be considered a programming reject.
21. Repeat steps 17 through 20 for all possible programming
locations
Post-Programming Read
22. Apply a voltage of V
CC2
= 4.0V to V
CC
(pin 24).
23. After a delay of tD, apply a voltage of V
IH
to E (pin 18).
24. Apply the correct binary address of the word to be read.
25. After a delay of TAVEL, apply a voltage of V
IL
to E (pin
18).
26. After a delay of TELQV, examine the outputs for correct
data. If any location fails to verify correctly, the PROM
should be considered a programming reject.
27. Repeat steps 23 through 26 for all address locations.
28. Apply a voltage of V
CC2
= 6.0V to V
CC
(pin 24).
29. Repeat steps 23 through 26 for all address locations.
6-3
HM-6617
Background Information HM-6617 Programming
Programming Specifications
SYMBOL
V
IL
V
IH
VCCPROG
V
CC1
V
CC2
tD
tR
tF
TEHEL
TAVEL
TELQV
tPW
tIP
IOP
Rn
T
A
NOTES:
1. All inputs must track V
CC
(pin 24) within these limits.
2. VCCPROG must be capable of supplying 500mA.
3. See Steps 22 through 29 of the Programming Algorithm.
4. See Step 11 of the Programming Algorithm.
5. All outputs should be pulled up to V
CC
through a resistor of value Rn.
6. Except during programming (See Programming Cycle Waveforms).
Input “0”
Voltage “1” (Note 6)
Programming V
CC
(Note 2)
Operating V
CC
Special Verify V
CC
(Note 3)
Delay Time
Rise Time
Fall Time
Chip Enable Pulse Width
Address Valid to Chip Enable Low Time
Chip Enable Low to Output Valid Time
Programming Pulse Width (Note 4)
Input Leakage at V
CC
= VCCPROG
Data Output Current at V
CC
= VCCPROG
Output Pull-Up Resistor (Note 5)
Ambient Temperature
PARAMETER
MIN
0.0
VCC-2
12.0
4.5
4.0
1.0
1.0
1.0
50
20
-
90
-10
-
5
-
TYP
0.2
V
CC
12.0
5.5
-
1.0
10.0
10.0
-
-
-
100
+1.0
-5.0
10
25
MAX
0.8
VCC+0.3
12.5
5.5
6.0
-
10.0
10.0
-
-
120
110
10
-10
15
-
UNITS
V
V
V
V
V
µs
µs
µs
ns
ns
ns
µs
µA
mA
kΩ
o
C
6-5
Power technology
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