K4S510632C
CMOS SDRAM
Stacked 512Mbit SDRAM
32M x 4bit x 4 Banks
Synchronous DRAM
LVTTL
Revision 0.1
Sept. 2001
* Samsung Electronics reserves the right to change products or specification without
Rev.0.1 Sept.2001
K4S510632C
CMOS SDRAM
Revision History
Revision 0.0 (Mar., 2001)
Revision 0.1 (Sept, 2001)
•
•
Redefined IDD1 & IDD4 in DC Characteristics
Changed the Notes in Operating AC Parameter.
< Before >
5. For 1H/1L, tRDL=1CLK and tDAL=1CLK+tRP is also supported .
SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP.
< After >
5.In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported.
SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP.
Rev.0.1 Sept.2001
K4S510632C
32M x 4Bit x 4 Banks Synchronous DRAM
FEATURES
• JEDEC standard 3.3V power supply
• LVTTL compatible with multiplexed address
• Four banks operation
• MRS cycle with address key programs
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system
clock.
• Burst read single-bit write operation
• DQM for masking
• Auto & self refresh
• 64ms refresh period (8K Cycle)
Part No.
K4S510632C-TC/L7C
K4S510632C-TC/L75
K4S510632C-TC/L1H
K4S510632C-TC/L1L
CMOS SDRAM
GENERAL DESCRIPTION
The K4S510632C is 536,870,912 bits synchronous high data rate
Dynamic RAM organized as 4 x 33,554,432 words by 4 bits, fabri-
cated with SAMSUNG's high performance CMOS technology. Syn-
chronous design allows precise cycle control with the use of
system clock I/O transactions are possible on every clock cycle.
Range of operating frequencies, programmable burst length and
programmable latencies allow the same device to be useful for a
variety of high bandwidth, high performance memory system appli-
cations.
ORDERING INFORMATION
Max Freq.
133MHz(CL=2)
133MHz(CL=3)
100MHz(CL=2)
100MHz(CL=3)
LVTTL
54pin
TSOP(II)
Interface Package
FUNCTIONAL BLOCK DIAGRAM
CLK,CAS,RAS
/WE,CKE,DQM
/CS1
64Mx4
64Mx4
/CS0
DQ0 ~ DQ3
A0~A12,BA0,BA1
* Samsung Electronics reserves the right to change products or specification without notice.
Staktek’ stacking technology is Samsung’ stacking technology of choice.
s
s
Rev.0.1 Sept.2001
K4S510632C
PIN CONFIGURATION (Top view)
V
DD
N.C
V
DDQ
N.C
DQ0
V
SSQ
N.C
N.C
V
DDQ
N.C
DQ1
V
SSQ
N.C
V
DD
CS1
WE
CAS
RAS
CS0
BA0
BA1
A10/AP
A0
A1
A2
A3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V
SS
N.C
V
SSQ
N.C
DQ3
V
DDQ
N.C
N.C
V
SSQ
N.C
DQ2
V
DDQ
N.C
V
SS
N.C/RFU
DQM
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
A4
V
SS
CMOS SDRAM
54Pin TSOP (II)
(400mil x 875mil)
(0.8 mm Pin pitch)
PIN FUNCTION DESCRIPTION
Pin
CLK
CS0~1
Name
System clock
Chip select
Input Function
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
Row/column addresses are multiplexed on the same pins.
Row address : RA
0
~ RA
12
, Column address : CA
0
~ CA
9,
CA
11
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
Makes data output Hi-Z, t
SHZ
after the clock and masks the output.
Blocks data input when DQM active.
Data inputs/outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide improved noise
immunity.
CKE
Clock enable
A
0
~ A
12
BA
0
~ BA
1
RAS
CAS
WE
DQM
DQ
0
~
3
V
DD
/V
SS
V
DDQ
/V
SSQ
Address
Bank select address
Row address strobe
Column address strobe
Write enable
Data input/output mask
Data input/output
Power supply/ground
Data output power/ground
Rev.0.1 Sept.2001
K4S510632C
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to Vss
Voltage on V
DD
supply relative to Vss
Storage temperature
Power dissipation
Short circuit current
Symbol
V
IN
, V
OUT
V
DD
, V
DDQ
T
STG
P
D
I
OS
Value
-1.0 ~ 4.6
-1.0 ~ 4.6
-55 ~ +150
2
50
CMOS SDRAM
Unit
V
V
°C
W
mA
Note : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to V
SS
= 0V, T
A
= 0 to 70°C)
Parameter
Supply voltage
Input logic high voltage
Input logic low voltage
Output logic high voltage
Output logic low voltage
Input leakage current
Symbol
V
DD
, V
DDQ
V
IH
V
IL
V
OH
V
OL
I
LI
Min
3.0
2.0
-0.3
2.4
-
-10
Typ
3.3
3.0
0
-
-
-
Max
3.6
V
DD
+0.3
0.8
-
0.4
10
Unit
V
V
V
V
V
uA
1
2
I
OH
= -2mA
I
OL
= 2mA
3
Note
Notes : 1. V
IH
(max) = 5.6V AC. The overshoot voltage duration is
≤
3ns.
2. V
IL
(min) = -2.0V AC. The undershoot voltage duration is
≤
3ns.
3. Any input 0V
≤
V
IN
≤
V
DDQ
.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
CAPACITANCE
Clock
RAS, CAS, WE, DQM
Address,CKE
CS0~1
DQ
0
~ DQ
8
(V
DD
= 3.3V, T
A
= 23°C, f = 1MHz, V
REF
=1.4V
±
200 mV)
Pin
Symbol
C
CLK
C
IN
C
ADD
C
cs
C
OUT
Min
5.0
5.0
5.0
2.5
8.0
Max
9.0
10.0
10.0
6.5
14.0
Unit
pF
pF
pF
pF
pF
Note
Rev.0.1 Sept.2001
京公网安备 11010802033920号
EEWORLD
