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HY27UH088G2M-MPIB

Description
Flash, 1GX8, 30ns, PBGA52, 12 X 17 MM, 1 MM HEIGHT, LEAD FREE, TLGA-52
Categorystorage    storage   
File Size437KB,53 Pages
ManufacturerSK Hynix
Websitehttp://www.hynix.com/eng/
Environmental Compliance
Download Datasheet Parametric View All

HY27UH088G2M-MPIB Overview

Flash, 1GX8, 30ns, PBGA52, 12 X 17 MM, 1 MM HEIGHT, LEAD FREE, TLGA-52

HY27UH088G2M-MPIB Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerSK Hynix
Parts packaging codeLGA
package instructionVFLGA,
Contacts52
Reach Compliance Codeunknown
ECCN code3A991.B.1.A
Maximum access time30 ns
JESD-30 codeR-PBGA-B52
length17 mm
memory density8589934592 bit
Memory IC TypeFLASH
memory width8
Number of functions1
Number of terminals52
word count1073741824 words
character code1000000000
Operating modeASYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize1GX8
Package body materialPLASTIC/EPOXY
encapsulated codeVFLGA
Package shapeRECTANGULAR
Package formGRID ARRAY, VERY THIN PROFILE, FINE PITCH
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)260
Programming voltage3.3 V
Certification statusNot Qualified
Maximum seat height1 mm
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)2.7 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal formBUTT
Terminal locationBOTTOM
Maximum time at peak reflow temperature20
typeSLC NAND TYPE
width12 mm
Base Number Matches1
HY27UH088G(2/D)M Series
8Gbit (1Gx8bit) NAND Flash
Document Title
8Gbit (1Gx8bit) NAND Flash Memory
Revision History
Revision
No.
0.0
Initial Draft.
1) Add Errata
tWH
tWP
25
35
tWC
50
60
History
Draft Date
May. 13. 2005
Remark
Preliminary
0.1
Specification
Relaxed
value
15
20
May. 23. 2005
Preliminary
1) Correct the valid Blocks Number.
Valid Blocks (max)
0.2
Before
After
8,196
8,192
Jun. 13. 2005
Preliminary
1) Add tRSBY (Table11)
- tRSBY (Dummy Busy Time for Cache Read)
0.3
- tRSBY is 5us (typ.)
2) Edit figure 18, 19
3) Correct Extended Read Status Register Commands (Table. 19)
1) Add TLGA package
- Figures & texts are added.
2) Correct the test Conditions (DC Characteristics table)
Test Conditions (
I
LI,
I
LO
)
VIN=VOUT=0 to 3.6V
Jun. 14. 2005
Preliminary
0.4
VIN=VOUT=0 to Vcc (max)
Sep. 16. 2005
Preliminary
3) Change AC Conditions table
4) Add tWW parameter ( tWW = 100ns, min)
- Texts & Figures are added.
- tWW is added in AC timing characteristics table.
5) Edit System Interface Using CE don’t care Figures.
6) Correct Address Cycle Map.
Rev 0.7 / Feb. 2006
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