PRELIMINARY
Am29LV640D/Am29LV641D
64 Megabit (4 M x 16-Bit) CMOS 3.0 Volt-only
Uniform Sector Flash Memory with VersatileI/O™ Control
DISTINCTIVE CHARACTERISTICS
s
Single power supply operation
— 3.0 to 3.6 volt read, erase, and program operations
s
VersatileI/O™ control
— Device generates data output voltages and tolerates
data input voltages as determined by the voltage on
the V
IO
pin
s
High performance
— Access times as fast as 90 ns
s
Manufactured on 0.23 µm process technology
s
CFI (Common Flash Interface) compliant
— Provides device-specific information to the system,
allowing host software to easily reconfigure for
different Flash devices
s
SecSi™ (Secured Silicon) Sector region
— 128-word sector for permanent, secure identification
through an 8-word random Electronic Serial Number
— May be programmed and locked at the factory or by
the customer
— Accessible through a command sequence
s
Ultra low power consumption (typical values at 3.0 V,
5 MHz)
— 9 mA typical active read current
— 26 mA typical erase/program current
— 200 nA typical standby mode current
s
Flexible sector architecture
— One hundred twenty-eight 32 Kword sectors
s
Sector Protection
— A hardware method to lock a sector to prevent
program or erase operations within that sector
— Sectors can be locked in-system or via programming
equipment
— Temporary Sector Unprotect feature allows code
changes in previously locked sectors
s
Embedded Algorithms
— Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
— Embedded Program algorithm automatically writes
and verifies data at specified addresses
s
Compatibility with JEDEC standards
— Pinout and software compatible with single-power
supply Flash
— Superior inadvertent write protection
s
Minimum 1 million erase cycle guarantee per sector
s
Package options
— 48-pin TSOP (Am29LV641DH/DL only)
— 56-pin SSOP (Am29LV640DH/DL only)
— 63-ball FBGA (Am29LV640DU only)
s
Erase Suspend/Erase Resume
— Suspends an erase operation to read data from, or
program data to, a sector that is not being erased,
then resumes the erase operation
s
Data# Polling and toggle bits
— Provides a software method of detecting program or
erase operation completion
s
Unlock Bypass Program command
— Reduces overall programming time when issuing
multiple program command sequences
s
Ready/Busy# pin (RY/BY#) (Am29LV640DU in FBGA
package only)
— Provides a hardware method of detecting program or
erase cycle completion
s
Hardware reset pin (RESET#)
— Hardware method to reset the device for reading array
data
s
WP# pin (Am29LV641DH/DL in TSOP,
Am29LV640DH/DL in SSOP only)
— At V
IL
, protects the first or last 32 Kword sector,
regardless of sector protect/unprotect status
— At V
IH
, allows removal of sector protection
— An internal pull up to V
CC
is provided
s
ACC pin
— Accelerates programming time for higher throughput
during system production
s
Program and Erase Performance (V
HH
not applied to
the ACC input pin)
— Word program time: 11 µs typical
— Sector erase time: 1.6 s typical for each 32 Kword
sector
This Data Sheet states AMD’s current technical specifications regarding the Products described herein. This Data
Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
Publication#
22366
Rev:
B
Amendment/+2
Issue Date:
October 18, 2000
Refer to AMD’s Website (www.amd.com) for the latest information.
P R E L I M I N A R Y
GENERAL DESCRIPTION
The Am29LV640DU/Am29LV641DU is a 64 Mbit, 3.0
Volt (3.0 V to 3.6 V) single power supply flash memory
devices organized as 4,194,304 words. Data appears
on DQ0-DQ15. The device is designed to be pro-
grammed in-system with the standard system 3.0 volt
V
CC
supply. A 12.0 volt V
PP
is not required for program
or erase operations. The device can also be pro-
grammed in standard EPROM programmers.
Access times of 90 and 120 ns are available for appli-
cations where V
IO
< V
CC
. Access times of 100 and 120
ns are available for applications where V
IO
≥
V
CC
. The
device is offered in 48-pin TSOP, 56-pin SSOP, and
63-ball FBGA packages. To eliminate bus contention
each device has separate chip enable (CE#), write en-
able (WE#) and output enable (OE#) controls.
Each device requires only a
single 3.0 Volt power
supply
(3.0 V to 3.6 V) for both read and write func-
tions. Internally generated and regulated voltages are
provided for the program and erase operations.
The device is entirely command set compatible with
the
JEDEC single-power-supply Flash standard.
Commands are written to the command register using
standard microprocessor write timing. Register con-
tents serve as inputs to an internal state-machine that
controls the erase and programming circuitry. Write
cycles also internally latch addresses and data
needed for the programming and erase operations.
Reading data out of the device is similar to reading
from other Flash or EPROM devices.
Device programming occurs by executing the program
command sequence. This initiates the
Embedded
Program
algorithm—an internal algorithm that auto-
matically times the program pulse widths and verifies
proper cell margin. The Unlock Bypass mode facili-
tates faster programming times by requiring only two
write cycles to program data instead of four.
Device erasure occurs by executing the erase com-
mand sequence. This initiates the
Embedded Erase
algorithm—an internal algorithm that automatically
preprograms the array (if it is not already programmed)
before executing the erase operation. During erase,
the device automatically times the erase pulse widths
and verifies proper cell margin.
The
VersatileI/O™
(V
IO
) control allows the host sys-
tem to set the voltage levels that the device generates
at its data outputs and the voltages tolerated at its data
inputs to the same voltage level that is asserted on the
V
IO
pin. This allows the device to operate in 1.8 V, 3 V,
or 5 V system environment as required.
The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, by reading the DQ7 (Data# Polling), or DQ6 (tog-
gle)
status bits.
After a program or erase cycle has
been completed, the device is ready to read array data
or accept another command.
The
sector erase architecture
allows memory sec-
tors to be erased and reprogrammed without affecting
the data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection
measures include a low
V
CC
detector that automatically inhibits write opera-
tions during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of sectors of memory.
This can be achieved in-system or via programming
equipment.
The
Erase Suspend/Erase Resume
feature enables
the user to put erase on hold for any period of time to
read data from, or program data to, any sector that is
not selected for erasure. True background erase can
thus be achieved.
The
hardware RESET# pin
terminates any operation
in progress and resets the internal state machine to
reading array data. The RESET# pin may be tied to
the system reset circuitry. A system reset would thus
also reset the device, enabling the system micropro-
cessor to read boot-up firmware from the Flash mem-
ory device.
The device offers a
standby mode
as a power-saving
feature. Once the system places the device into the
standby mode power consumption is greatly reduced.
The
SecSi™ (Secured Silicon) Sector
provides an
minimum 128-word area for code or data that can be
permanently protected. Once this sector is protected,
no further programming or erasing within the sector
can occur.
The
Write Protect (WP#)
feature protects the first or
last sector by asserting a logic low on the WP# pin.
The protected sector will still be protected even during
accelerated programming.
The
accelerated program (ACC)
feature allows the
system to program the device at a much faster rate.
When ACC is pulled high to V
HH
, the device enters the
Unlock Bypass mode, enabling the user to reduce the
time needed to do the program operation. This feature
is intended to increase factory throughput during sys-
tem production, but may also be used in the field if de-
sired.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective-
ness. The device electrically erases all bits within a
sector simultaneously via Fowler-Nordheim tunnelling.
The data is programmed using hot electron injection.
2
Am29LV640D/Am29LV641D
P R E L I M I N A R Y
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 5
Special Handling Instructions for FBGA Package .. 7
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 9
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 10
Table 1. Device Bus Operations .................................10
DQ2: Toggle Bit II ................................................. 31
Reading Toggle Bits DQ6/DQ2 ............................ 31
DQ5: Exceeded Timing Limits .............................. 31
DQ3: Sector Erase Timer ..................................... 31
Table 11. Write Operation Status ................................32
VersatileI/O™ (V
IO
) Control ................................... 10
Requirements for Reading Array Data ................. 10
Writing Commands/Command Sequences .......... 11
Standby Mode ...................................................... 11
Automatic Sleep Mode ......................................... 11
RESET#: Hardware Reset Pin ............................. 11
Output Disable Mode ............................................ 12
Table 2. Sector Address Table ....................................12
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 33
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . 33
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 34
CMOS Compatible ............................................... 34
Zero-Power Flash ................................................. 35
Figure 9. I
CC1
Current vs. Time (Showing
Active and Automatic Sleep Currents) ........................ 35
Figure 10. Typical I
CC1
vs. Frequency ......................... 35
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 11. Test Setup................................................. 36
Table 12. Test Specifications ......................................36
Key to Switching Waveforms. . . . . . . . . . . . . . . . 36
Figure 12. Input Waveforms and
Measurement Levels ................................................... 36
Autoselect Mode ................................................... 16
Table 3. Autoselect Codes, (High Voltage Method) ...16
Sector Group Protection and Unprotection .......... 17
Table 4. Sector Group Protection/Unprotection
Address Table ............................................................17
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 37
Read-Only Operations ......................................... 37
Figure 13. Read Operation Timings ............................ 37
Write Protect (WP#) ............................................. 18
Temporary Sector Group Unprotect ..................... 18
Figure 1. Temporary Sector Group
Unprotect Operation.................................................... 18
Figure 2. In-System Sector Group
Protect/Unprotect Algorithms ...................................... 19
Hardware Reset (RESET#) .................................. 38
Figure 14. Reset Timings ............................................ 38
Erase and Program Operations ............................ 39
Figure 15. Program Operation Timings ....................... 40
Figure 16. Accelerated Program Timing Diagram ....... 40
Figure 17. Chip/Sector Erase Operation Timings........ 41
Figure 18. Data# Polling Timings
(During Embedded Algorithms) ................................... 42
Figure 19. Toggle Bit Timings
(During Embedded Algorithms) ................................... 43
Figure 20. DQ2 vs. DQ6.............................................. 43
SecSi™ (Secured Silicon) Sector Flash
Memory Region .................................................... 20
Table 5. SecSi Sector Contents ..................................20
Hardware Data Protection .................................... 20
Common Flash Memory Interface (CFI) . . . . . . . 21
Table 6. CFI Query Identification String ......................
System Interface String...............................................
Table 8. Device Geometry Definition ..........................
Table 9. Primary Vendor-Specific Extended Query ....
21
22
22
23
Temporary Sector Unprotect ................................ 44
Figure 21. Temporary Sector Group Unprotect
Timing Diagram ........................................................... 44
Figure 22. Sector Group Protect and Unprotect
Timing Diagram ........................................................... 45
Command Definitions . . . . . . . . . . . . . . . . . . . . . 23
Reading Array Data .............................................. 23
Reset Command .................................................. 24
Autoselect Command Sequence .......................... 24
Enter SecSi Sector/Exit SecSi Sector
Command Sequence ............................................ 24
Word Program Command Sequence ................... 24
Figure 3. Program Operation ...................................... 25
Alternate CE# Controlled Erase and
Program Operations ............................................. 46
Figure 23. Alternate CE# Controlled Write
(Erase/Program) Operation Timings ........................... 47
Chip Erase Command Sequence ......................... 25
Sector Erase Command Sequence ...................... 26
Erase Suspend/Erase Resume Commands ......... 26
Figure 4. Erase Operation........................................... 27
Table 10. Command Definitions.................................. 28
Write Operation Status . . . . . . . . . . . . . . . . . . . . . 29
DQ7: Data# Polling ............................................... 29
Figure 5. Data# Polling Algorithm ............................... 29
RY/BY#: Ready/Busy# ......................................... 30
DQ6: Toggle Bit I .................................................. 30
Figure 6. Toggle Bit Algorithm..................................... 30
Erase And Programming Performance . . . . . . . 48
Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 48
TSOP Pin Capacitance . . . . . . . . . . . . . . . . . . . . . 48
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 49
SSO056—56-Pin Shrink Small Outline Package
(SSOP) ................................................................. 49
FBE063—63-Ball Fine-Pitch Ball Grid Array
(FBGA) 11 x 12 mm ............................................. 50
TS 048—48-Pin Standard TSOP ......................... 51
TSR048—48-Pin Reverse TSOP ......................... 52
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 53
Revision B+2 (October 18, 2000) ......................... 54
Am29LV640D/Am29LV641D
3
P R E L I M I N A R Y
PRODUCT SELECTOR GUIDE
Part Number
Speed Option
Max Access Time (ns)
CE# Access Time (ns)
OE# Access Time (ns)
V
CC
= 3.0–3.6 V, V
IO
= 3.0–5.0 V
V
CC
= 3.0–3.6 V, V
IO
= 1.8–2.9 V
90
90
35
90R
101R
100
100
35
Am29LV640D/Am29LV641D
120R
121R
120
120
50
Note:
See “AC Characteristics” for full specifications.
BLOCK DIAGRAM
RY/BY# (Note 1)
V
CC
V
SS
RESET#
Erase Voltage
Generator
V
IO
Input/Output
Buffers
Sector Switches
DQ0
–
DQ15
WE#
WP#
(Note 2)
ACC
State
Control
Command
Register
PGM Voltage
Generator
Chip Enable
Output Enable
Logic
STB
Data
Latch
CE#
OE#
STB
V
CC
Detector
Timer
Address Latch
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
A0–A21
Notes:
1. RY/BY# is only available in the FBGA package.
2. WP# is only available in the TSOP and SSOP packages.
4
Am29LV640D/Am29LV641D
P R E L I M I N A R Y
CONNECTION DIAGRAMS
A15
A14
A13
A12
A11
A10
A9
A8
A21
A20
WE#
RESET#
ACC
WP#
A19
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48-Pin Standard TSOP
(Am29LV641DH/DL only)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
V
IO
V
SS
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V
CC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
V
SS
CE#
A0
A16
V
IO
V
SS
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V
CC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
V
SS
CE#
A0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48-Pin Reverse TSOP
(Am29LV641DH/DL only)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A15
A14
A13
A12
A11
A10
A9
A8
A21
A20
WE#
RESET#
ACC
WP#
A19
A18
A17
A7
A6
A5
A4
A3
A2
A1
Am29LV640D/Am29LV641D
5
Microcontroller MCU
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