MITSUBISHI MICROCOMPUTERS
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4282 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
DESCRIPTION
The 4282 Group enables fabrication of 8
×
7 key matrix and has
the followin timers;
• an 8-bit timer which can be used to set each carrier wave and
has two reload register
• an 8-bit timer which can be used to auto-control and has a
reload register.
FEATURES
• Number of basic instructions ............................................. 68
• Minimum instruction execution time ............................ 8.0
µ
s
(at f(X
IN
) = 4.0 MHz, system clock = f(X
IN
)/8)
• Supply voltage ................................................. 1.8 V to 3.6 V
• Subroutine nesting ..................................................... 4 levels
• Timer
Timer 1 ................................................................... 8-bit timer
(This has a reload register and carrier wave output auto-control
function)
Timer 2 ................................................................... 8-bit timer
(This has two reload registers and carrier wave output function)
• Logic operation function (XOR, OR, AND)
• RAM back-up function
• Key-on wakeup function (ports D
4
–D
7
, E
0
–E
2
, G
0
–G
3
) .... 11
• I/O port (ports D, E, G, CARR) .......................................... 16
• Oscillation circuit ..................................... Ceramic resonance
• Watchdog timer
• Power-on reset circuit
• Voltage drop detection circuit ......................... Typical:1.50 V
(system reset)
APPLICATION
Various remote control transmitters
Product
M34282M1-XXXGP *
M34282M2-XXXGP *
M34282E2GP *
* : Under development (June, 2000)
ROM (PROM) size
(× 9 bits)
1024 words
2048 words
2048 words
RAM size
(× 4 bits)
48 words
64 words
64 words
Package
20P2E/F-A
20P2E/F-A
20P2E/F-A
ROM type
Mask ROM
Mask ROM
One Time PROM
PIN CONFIGURATION (TOP VIEW)
V
SS
E
2
E
1
X
IN
X
OUT
E
0
G
0
G
1
G
2
G
3
1
2
20
19
V
DD
CARR
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
M34282Mx-XXXGP
3
4
5
6
7
8
9
10
18
17
16
15
14
13
12
11
Outline 20P2E/F-A
2
ELI
PR
M
BLOCK DIAGRAM
1
2
4
4
4
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IN
I/O port
Port E
Port D
Port G
Internal peripheral function
System clock generation circuit
X
IN
-X
OUT
Timer/Remote-control carrier-wave output
Timer 1 (8 bits, carrier wave output control)
Timer 2 (8 bits, carrier wave generation)
Reset (voltage drop detection circuit)
Watchdog timer (14 bits)
MITSUBISHI
ELECTRIC
Memory
(Note)
ROM
(1024,2048 words
✕
9 bits)
720 series
CPU core
ALU(4 bits)
Register A (4 bits)
Register B (4 bits)
Register E (8 bits)
Register D (3 bits)
Stack register SK (4 levels)
RAM
(48,64 words
✕
4 bits)
MITSUBISHI MICROCOMPUTERS
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
4282 Group
Note: PROM 2048 words
✕
9 bits, RAM 64 words
✕
4 bits for built-in PROM version.
MITSUBISHI MICROCOMPUTERS
ELI
PR
.
.
tion hange
c
ifica
pec ject to
s
ub
inal
t a f are s
s no limits
i
his tric
e
e: T
otic param
N
ome
S
M
ARY
IN
4282 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
PERFORMANCE OVERVIEW
Parameter
Number of basic instructions
Function
68
Minimum instruction execution time 8.0
µ
s (f(X
IN
) = 4.0 MHz, system clock = f(X
IN
)/8, V
DD
= 3 V)
Memory sizes ROM M34282M2/E2 2048 words
✕
9 bits
RAM
Input/Output
ports
1024 words
✕
9 bits
M34282M1
M34282M2/E2 64 words
✕
4 bits
48 words
✕
4 bits
M34282M1
Four independent output ports
Four independent I/O ports with the pull-down function
3-bit input port with the pull-down function
2-bit output port (E
0
, E
1
)
4-bit I/O port with the pull-down function
1-bit output port; CMOS output
8-bit timer with a reload register
8-bit timer with two reload registers
4 levels (However, only 3 levels can be used when the TABP p instruction is executed)
CMOS silicon gate
20-pin plastic molded SSOP (20P2E/F-A)
–20 °C to 85 °C
1.8 V to 3.6 V
400
µA
(f(X
IN
) = 4.0 MHz, system clock = f(X
IN
)/8, V
DD
= 3 V)
D
0
–D
3
Output
D
4
–D
7
I/O
E
0
–E
2
Input
E
0
, E
1
Output
G
0
–G
3
I/O
CARR Output
Timer
Timer 1
Timer 2
Subroutine nesting
Device structure
Package
Operating temperature range
Supply voltage
Power
Active mode
dissipation
(typical value) RAM back-up mode 0.1
µ
A (at room temperature, V
DD
= 3 V)
PIN DESCRIPTION
Pin
V
DD
V
SS
X
IN
X
OUT
D
0
–D
3
D
4
–D
7
Name
Power supply
Ground
System clock input
System clock output
Output port D
I/O port D
Input/Output
Function
—
Connected to a plus power supply.
—
Input
Output
Output
I/O
Connected to a 0 V power supply.
I/O pins of the system clock generating circuit. Connect a ceramic resonator
between pins X
IN
and X
OUT
. The feedback resistor is built-in between pins X
IN
and X
OUT
.
Each pin of port D has an independent 1-bit wide output function. The output
structure is P-channel open-drain.
1-bit I/O port. For input use, set the latch of the specified bit to “0.” When the built-
in pull-down transistor is turned on, the key-on wakeup function using “H” level
sense and the pull-down transistor become valid. The output structure is P-channel
open-drain.
E
0
–E
2
I/O port E
Output
Input
2-bit (E
0
, E
1
) output port. The output structure is P-channel open-drain.
3-bit input port. For input use (E
0
, E
1
), set the latch of the specified bit to “0.”
When the built-in pull-down transistor is turned on, the key-on wakeup function
using “H” level sense and the pull-down transistor become valid. Port E
2
has an
input-only port and has a key-on wakeup function using “H” level sense and pull-
down transistor.
G
0
–G
3
I/O port G
I/O
4-bit I/O port. For input use, set the latch of the specified bit to “0.” The output structure
is P-channel open-drain. When the built-in pull-down transistor is turned on, the key-
on wakeup function using “H” level sense and pull-down transistor become valid.
CARR
Carrier wave output
for remote control
Output
Carrier wave output pin for remote control. The output structure is CMOS circuit.
MITSUBISHI
ELECTRIC
3
MITSUBISHI MICROCOMPUTERS
ELI
PR
.
ion. hange
icat
ecif ect to c
p
al s subj
a fin
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not mits ar
is
his tric li
T
me
ice:
Not e para
m
So
M
ARY
IN
4282 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
CONNECTIONS OF UNUSED PINS
Pin
D
0
–D
7
E
0
, E
1
E
2
G
0
–G
3
Connection
Open or connect to V
DD
pin (Note 1).
Set the output latch to “1” and open, or
connect to V
DD
pin (Note 2).
Open or connect to V
SS
pin.
Set the output latch to “1” and open, or
connect to V
DD
pin (Note 2).
Notes 1: Ports D
4
–D
7
: Set the bit 2 (PU0
2
) of the pull-down control register PU1 to “0” by software and turn the pull-down transistor
OFF.
2: Set the corresponding bits of the pull-down control register PU0 to “0” by software and turn the pull-down transistor OFF.
(Note in order to set the output latch to “1” to make pins open)
• After system is released from reset, a port is in a high-impedance state until the output latch of the port is set to “1” by software.
Accordingly, the voltage level of pins is undefined and the excess of the supply current may occur.
• To set the output latch periodically is recommended because the value of output latch may change by noise or a program run away
(caused by noise).
(Note when connecting to V
SS
and V
DD
)
• Connect the unused pins to V
SS
or V
DD
at the shortest distance and use the thick wire against noise.
PORT FUNCTION
Port
Port D
Pin
D
0
–D
3
Input/
Output
Output structure
Control
bits
1 bit
Control
instructions
SD
RD
CLD
SD
RD
CLD
SZD
Port E
E
0
E
1
E
2
Port G
G
0
–G
3
I/O
(2)
Input
(1)
I/O
(4)
Port CARR
CARR
Output CMOS
(1)
1 bit
P-channel open-drain
P-channel open-drain
Output: OEA
2 bits
Input:
3 bits
4 bits
IAE
IAE
OGA
IAG
SCAR
RCAR
PU0
Pull-down function and
key-on wakeup function
(programmable)
PU0
PU1
Pull-down function and
key-on wakeup function
(programmable)
Pull-down function and
key-on wakeup function
(programmable)
Control
registers
Remark
Output P-channel open-drain
(4)
I/O
(4)
D
4
–D
7
DEFINITION OF CLOCK AND CYCLE
• System clock (STCK)
The system clock is the source clock for controlling this product.
It can be selected as shown below whether to use the CCK
instruction.
CCK instruction
When not using
When using
System clock
f(X
IN
)/8
f(X
IN
)
Instruction clock
f(X
IN
)/32
f(X
IN
)/4
• Instruction clock (INSTCK)
The instruction clock is a signal derived by dividing the system
clock by 4, and is the basic clock for controlling CPU. The one
instruction clock cycle is equivalent to one machine cycle.
• Machine cycle
The machine cycle is the cycle required to execute the
instruction.
4
MITSUBISHI
ELECTRIC
MITSUBISHI MICROCOMPUTERS
ELI
PR
.
.
tion hange
c
ifica
pec ject to
s
ub
inal
t a f are s
s no limits
i
his tric
e
e: T
otic param
N
ome
S
M
ARY
IN
4282 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
PORT BLOCK DIAGRAMS
Register Y
SD instruction
RD instruction
Decoder
(Note 1)
S
R
CLD instruction
Q
Ports D
0
–D
3
Register Y
SD instruction
RD instruction
Decoder
(Note 1)
S Q
R
Ports D
4
–D
7
(Note 5)
CLD instruction
Skip decision (SZD instruction)
Key-on wakeup
(Note 2) PU1
i
Register A
A
j
(Note 3)
A
j
Key-on wakeup input
(Note 3) PU0
j
IAE instruction
Register A
A
2
Key-on wakeup input
Pull-down
transistor
Pull-down
transistor
D Q
OEA
instruction
IAE instruction
T
(Note 1)
Pull-down transistor
Ports E
0
, E
1
(Note 5)
Port E
2
(Note 5)
(Note 1)
Register A
A
j
(Note 3)
A
j
Key-on wakeup input
PU0
2
Register A
A
k
(Note 4)
A
k
Key-on wakeup input
Pull-down transistor
PU0
3
CAR flag
SCAR instruction
RCAR instruction
CARRYD
(from timer 2)
S Q
R
OGA
instruction
D Q
T
IAG instruction
Pull-down transistor
OGA
instruction
D Q
T
IAG instruction
(Note 1)
Ports G
0
, G
1
(Note 5)
(Note 1)
Ports G
2
, G
3
(Note 5)
CARRY
(to timer 1)
(Note 1)
Port CARR
Timer 1 underflow signal
V1
2
D Q
T R
V1
0
Carrier wave output control signal
Notes 1:
This symbol represents a parasitic diode.
2: i represents bits 0 to 3.
3: j represents bits 0, 1.
4: k represents bits 2, 3.
5: Applied voltage must be less than VDD.
MITSUBISHI
ELECTRIC
5
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