M312L6423ETS datasheet, PDF - EEWORLD Datasheet

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M312L6423ETS: DescriptionDDR SDRAM Registered Module; File Size451KB，23 Pages; ManufacturerSAMSUNG; Websitehttp://www.samsung.com/Products/Semiconductor/

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DDR SDRAM Registered Module

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256MB, 512MB, 1GB Registered DIMM

DDR SDRAM

DDR SDRAM Registered Module

184pin Registered Module based on 256Mb E-die (x4, x8)

with 1,700 / 1,200mil Height & 72-bit ECC

Revision 1.4

January, 2004

Revision 1.4 February, 2004

256MB, 512MB, 1GB Registered DIMM

Revision History

Revision 1.0 (April, 2003)

- First release

Revision 1.1 (July, 2003)

- Delete speed B3

Revision 1.2 (August, 2003)

- Corrected typo.

Revision 1.3 (January, 2004)

- Corrected typo in functional block diagram of 1GB DIMM

Revision 1.4 (February, 2004)

- Corrected functional block diagram of 1GB DIMM

DDR SDRAM

Revision 1.4 February, 2004

256MB, 512MB, 1GB Registered DIMM

184Pin Registered DIMM based on 256Mb E-die (x4, x8)

Ordering Information

Part Number

M383L3223ETS-CAA/A2/B0/A0

M383L6423ETS-CAA/A2/B0/A0

M383L6420ETS-CAA/A2/B0/A0

M383L2828ET1-CAA/A2/B0/A0

M312L3223ETS-CAA/A2/B0/A0

M312L6423ETS-CAA/A2/B0/A0

M312L6420ETS-CAA/A2/B0/A0

M312L2828ET0-CAA/A2/B0/A0

Density

256MB

512MB

1GB

256MB

512MB

1GB

Organization

32M x 72

64M x 72

128M x 72

32M x 72

64M x 72

128M x 72

DDR SDRAM

Component Composition

32Mx8( K4H560838E) * 9EA

32Mx8( K4H560838E) * 18EA

64Mx4( K4H560438E) * 18EA

st.128Mx4( K4H510638E) * 18EA

32Mx8( K4H560838E) * 9EA

32Mx8( K4H560838E) * 18EA

64Mx4( K4H560438E) * 18EA

st.128Mx4( K4H510638E) * 18EA

Height

1,700mil

1,200mil

Operating Frequencies

AA(DDR266@CL=2)

Speed @CL2

Speed @CL2.5

CL-tRCD-tRP

133MHz

2-2-2

A2(DDR266@CL=2)

133MHz

2-3-3

B0(DDR266@CL=2.5)

100MHz

133MHz

2.5-3-3

A0(DDR200@CL=2)

100MHz

2-2-2

Feature

• Power supply : Vdd: 2.5V

0.2V, Vddq: 2.5V

0.2V

•

Double-data-rate architecture; two data transfers per clock cycle

• Bidirectional data strobe(DQS)

• Differential clock inputs(CK and CK)

• DLL aligns DQ and DQS transition with CK transition

• Programmable Read latency 2, 2.5 (clock)

• Programmable Burst length (2, 4, 8)

• Programmable Burst type (sequential & interleave)

• Edge aligned data output, center aligned data input

• Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh)

• Serial presence detect with EEPROM

• 1,700mil / 1,200mil height & double sided

SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.

Revision 1.4 February, 2004

256MB, 512MB, 1GB Registered DIMM

Pin Configuration (Front side/back side)

Front

VREF

DQ0

VSS

DQ1

DQS0

DQ2

VDD

DQ3

/RESET

VSS

DQ8

DQ9

DQS1

VDDQ

*CK1

*/CK1

VSS

DQ10

DQ11

CKE0

VDDQ

DQ16

DQ17

DQS2

VSS

DQ18

VDDQ

DQ19

Front

DQ24

VSS

DQ25

DQS3

VDD

DQ26

DQ27

VSS

CB0

CB1

VDD

DQS8

CB2

VSS

CB3

BA1

Front

VDDQ

/WE

DQ41

/CAS

VSS

DQS5

DQ42

DQ43

VDD

*/CS2

DQ48

DQ49

VSS

*CK2

*/CK2

VDDQ

DQS6

DQ50

DQ51

VSS

VDDID

DQ56

DQ57

VDD

DQS7

DQ58

DQ59

VSS

SDA

SCL

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

Back

VSS

DQ4

DQ5

VDDQ

DM0/DQS9

DQ6

DQ7

VSS

VDDQ

DQ12

DQ13

DM1/DQS10

VDD

DQ14

DQ15

CKE1

VDDQ

*BA2

DQ20

A12

VSS

DQ21

A11

DM2/DQS11

VDD

DQ22

DQ23

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

Back

VSS

DQ28

DQ29

VDDQ

DM3/DQS12

DQ30

VSS

DQ31

CB4

CB5

VDDQ

CK0

/CK0

VSS

DM8/DQS17

A10

CB6

VDDQ

CB7

DDR SDRAM

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

Back

/RAS

DQ45

VDDQ

/CS0

/CS1

DM5/DQS14

VSS

DQ46

DQ47

*/CS3

VDDQ

DQ52

DQ53

*A13

VDD

DM6/DQS15

DQ54

DQ55

VDDQ

DQ60

DQ61

VSS

DM7/DQS16

DQ62

DQ63

VDDQ

SA0

SA1

SA2

VDDSPD

KEY

DQ32

VDDQ

DQ33

DQS4

DQ34

VSS

BA0

DQ35

DQ40

KEY

VSS

DQ36

DQ37

VDD

DM4/DQS13

DQ38

DQ39

VSS

DQ44

Note :

1. * : These pins are not used in this module.

2. Pins 111, 158 are NC for 1row module[M383(12)L3223ETS, M383(12)L6420ETS] & used for 2row module [M383(12)L6423ETS,

M383(12)L2828ET1(0) ]

3. Pins 97, 107, 119, 129, 140, 149, 159, 169, 177 : DM (x8 base module) or DQS (x4 base module).

Pin Description

Pin Name

A0 ~ A12

BA0 ~ BA1

DQ0 ~ DQ63

DQS0 ~ DQS17

CK0,CK0 ~ CK2, CK2

CKE0, CKE1(for double banks)

CS0, CS1(for double banks)

RAS

CAS

CB0 ~ CB7

Function

Address input (Multiplexed)

Bank Select Address

Data input/output

Data Strobe input/output

Clock input

Clock enable input

Chip select input

Row address strobe

Column address strobe

Write enable

Check bit(Data-in/data-out)

Pin Name

DM0 ~ DM8

VDD

VDDQ

VSS

VREF

VDDSPD

SDA

SCL

SA0 ~ 2

Data - in mask

Power supply (2.5V)

Power Supply for DQS(2.5V)

Ground

Power supply for reference

Serial EEPROM Power/Supply ( 2.3V to 3.6V )

Serial data I/O

Serial clock

Address in EEPROM

No connection

Function

Revision 1.4 February, 2004

256MB, 512MB, 1GB Registered DIMM

DDR SDRAM

256MB, 32M x 72 ECC Module (M383(12)L3223ETS)

(Populated as 1 bank of x8 DDR SDRAM Module)

Functional Block Diagram

RCS0

DQS0

DM0

DM/

DQS

DQS4

DM4

DM/

DQS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQS1

DM1

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DQS5

DM5

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

DM/

DQS

DM/

DQS

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQS2

DM2

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

DQS6

DM6

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

DM/

DQS

DM/

DQS

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQS3

DM3

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DQS7

DM7

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

DM/

DQS

DM/

DQS

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DQS8

DM8

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

Serial PD

SCL

SA0

SA1

SA2

SDA

DM/

DQS

DDSPD

DDQ

SPD

D0 - D8

CB0

CB1

CB2

CB3

CB4

CB5

CB6

CB7

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

VREF

D0 - D8

PLL*

CK0,CK0

* Wire per Clock Loading table/wiring Diagrams

CS0

BA0-BA1

A0-A12

RAS

CAS

CKE0

PCK

RCS0

RBA0 - RBA1

RA0 - RA12

RRAS

RCAS

RCKE0

RWE

RESET

BA0 -BA1 : SDRAMs DQ0 - D8

A0 -A12 : SDRAMs D0 - D8

RAS : SDRAMs D0 - D8

CAS : SDRAMs D0 - D8

CKE : SDRAMs D0 - D8

WE: SDRAMs D0 - D8

Notes:

1. DQ-to-I/O wiring is shown as recom-

mended but may be changed.

2. DQ/DQS/DM/CKE/CS relationships

must be maintained as shown.

3. DQ, DQS, DM/DQS resistors: 22 Ohms.

Revision 1.4 February, 2004

M312L6423ETS Related Products

	M312L6423ETS	M383L6423ETS	M383L6420ETS	M383L3223ETS	M383L2828ET1	M312L6420ETS	M312L3223ETS	M312L2828ET0
Description	DDR SDRAM Registered Module	DDR SDRAM Registered Module	DDR SDRAM Registered Module	DDR SDRAM Registered Module	DDR SDRAM Registered Module	DDR SDRAM Registered Module	DDR SDRAM Registered Module	DDR SDRAM Registered Module

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Shortcut: 00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W

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