SI5342B-B05850-GMR datasheet, PDF

Datasheet> All Categories > The embedded processor and controller> Microcontrollers and processors> SI5342B-B05850-GMR

SI5342B-B05850-GMR: DescriptionProcessor Specific Clock Generator,; CategoryThe embedded processor and controller Microcontrollers and processors; File Size1MB，60 Pages; ManufacturerSilicon Laboratories Inc; Environmental Compliance

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SI5342B-B05850-GMR Overview

Processor Specific Clock Generator,

SI5342B-B05850-GMR Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Silicon Laboratories Inc
package instruction	HVQCCN,
Reach Compliance Code	unknown
JESD-30 code	S-XQCC-N44
length	7 mm
Number of terminals	44
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Maximum output clock frequency	350 MHz
Package body material	UNSPECIFIED
encapsulated code	HVQCCN
Package shape	SQUARE
Package form	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)	260
Master clock/crystal nominal frequency	750 MHz
Maximum seat height	0.9 mm
Maximum supply voltage	1.89 V
Minimum supply voltage	1.71 V
Nominal supply voltage	1.8 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	NO LEAD
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	7 mm
uPs/uCs/peripheral integrated circuit type	CLOCK GENERATOR, PROCESSOR SPECIFIC
Base Number Matches	1

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Si 5 3 4 5 / 4 4 /4 2

1 0 - C

H A N N E L

, A

-F

R E Q U E N C Y

, A

- O

U T P U T

I T T E R

T T E N U A T O R

LOC K

U LT IP L IE R

Features



Generates any combination of output



Optional zero delay mode

frequencies from any input frequency



Fastlock feature: 50 ms typ lock time

Input frequency range:



Glitchless on the fly output frequency



Differential: 8 kHz to 750 MHz

changes



LVCMOS: 8 kHz to 250 MHz



DCO mode: as low as 0.001 ppb

Output frequency range:

steps.



Differential: up to 712.5 MHz



Core voltage



LVCMOS: up to 250 MHz



: 1.8 V ±5%

Ultra-low jitter:



DDA

: 3.3 V ±5%

<100 fs typ (12 kHz–20 MHz)



Independent output supply pins: 3.3 V,

Programmable jitter attenuation

2.5 V, or 1.8 V

bandwidth from 0.1 Hz to 4 kHz



Output-output skew: <100 ps

Meets G.8262 EEC Opt 1, 2 (SyncE)



Serial interface: I

C or SPI

Highly configurable outputs compatible



In-circuit programmable with

with LVDS, LVPECL, LVCMOS, CML,

non-volatile OTP memory

and HCSL with programmable signal



ClockBuilder Pro

software simplifies

amplitude

device configuration

Status monitoring (LOS, OOF, LOL)



Si5345: 4 input, 10 output, 64 QFN

Hitless input clock switching:



Si5344: 4 input, 4 output, 44 QFN

automatic or manual



Si5342: 4 input, 2 output, 44 QFN

Locks to gapped clock inputs



Temperature range: –40 to +85 °C

Automatic free-run and holdover



Pb-free, RoHS-6 compliant

modes

Ordering Information:

See section 8

Functional Block Diagram

XTAL

Si5345/44/42

IN_SEL

Device Selector Guide

Grade

Si534xA

Si534xB

Si534xC

Si534xD

Max Output Frequency

712.5 MHz

350 MHz

712.5 MHz

350 MHz

Frequency Synthesis Modes

Integer+Fractional

Integer

OSC

IN0

IN1

IN2

IN3/

FB_IN

÷FRAC

Optional

External

Feedback

DSPLL

Applications



OTN Muxponders and Transponders

10/40/100G networking line cards

GbE/10GbE/100GbE Synchronous

Ethernet (ITU-T G.8262)



Carrier Ethernet switches

SONET/SDH Line Cards

Broadcast video

Test and measurement

ITU-T G.8262 (SyncE) Compliant

Multi

Synth

Multi

Synth

Multi

Synth

Multi

Synth

Multi

Synth

÷INT

OUT0

Si5342

Si5344

OUT1

OUT2

OUT3

OUT4

OUT5

OUT6

OUT7

OUT8

OUT9

Description

These jitter attenuating clock multipliers combine fourth-generation DSPLL and

MultiSynth™ technologies to enable any-frequency clock generation and jitter

attenuation for applications requiring the highest level of jitter performance. These

devices are programmable via a serial interface with in-circuit programmable non-

volatile memory (NVM) so they always power up with a known frequency configuration.

They support free-run, synchronous, and holdover modes of operation, and offer both

automatic and manual input clock switching. The loop filter is fully integrated on-chip,

eliminating the risk of noise coupling associated with discrete solutions. Further, the

jitter attenuation bandwidth is digitally programmable, providing jitter performance

optimization at the application level. Programming the Si5345/44/42 is easy with

Silicon Labs’

ClockBuilderPro

software. Factory preprogrammed devices are also

available.

NVM

C/SPI

Control/

Status

÷INT

Si5345

Preliminary Rev. 0.95 3/15

Si5345/44/42

This information applies to a product under development. Its characteristics and specifications are subject to change without notice.

Si5345/44/42

ABLE

ON TENTS

1. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

2. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

3. Typical Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4. Detailed Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5.1. Frequency Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5.2. DSPLL Loop Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5.3. Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5.4. External Reference (XA/XB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

5.5. Digitally Controlled Oscillator (DCO) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

5.6. Inputs (IN0, IN1, IN2, IN3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5.7. Fault Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

5.8. Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

5.9. Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

5.10. In-Circuit Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

5.11. Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

5.12. Custom Factory Preprogrammed Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

5.13. Enabling Features and/or Configuration Settings Unavailable in ClockBuilder Pro for

Factory Preprogrammed Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

6. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

6.1. Addressing Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

6.2. High-Level Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

7. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

8. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

8.1. Ordering Part Number Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

9. Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

9.1. Si5345 9x9 mm 64-QFN Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

9.2. Si5344 and Si5342 7x7 mm 44-QFN Package Diagram . . . . . . . . . . . . . . . . . . . . . . 55

10. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

11. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

12. Device Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

Preliminary Rev. 0.95

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