DSPB56362PV100 datasheet, PDF - EEWORLD Datasheet

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DSPB56362PV100: DescriptionIC,DSP,24-BIT,CMOS,QFP,144PIN,PLASTIC; CategoryThe embedded processor and controller Microcontrollers and processors; File Size2MB，152 Pages; ManufacturerNXP; Websitehttps://www.nxp.com; Environmental Compliance

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DSPB56362PV100 Overview

IC,DSP,24-BIT,CMOS,QFP,144PIN,PLASTIC

DSPB56362PV100 Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	conform to
Maker	NXP
Parts packaging code	QFP
package instruction	20 X 20 MM, 0.50 MM PITCH, 1.40 MM HEIGHT, PLASTIC, LQFP-144
Contacts	144
Reach Compliance Code	unknown
ECCN code	3A991
Address bus width	18
barrel shifter	YES
bit size	24
boundary scan	YES
maximum clock frequency	100 MHz
External data bus width	24
Format	FIXED POINT
Internal bus architecture	MULTIPLE
JESD-30 code	S-PQFP-G144
length	20 mm
low power mode	YES
Humidity sensitivity level	3
Number of terminals	144
Package body material	PLASTIC/EPOXY
encapsulated code	LFQFP
Encapsulate equivalent code	QFP144,.87SQ,20
Package shape	SQUARE
Package form	FLATPACK, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	3.3 V
Certification status	Not Qualified
RAM (number of words)	11264
Maximum seat height	1.6 mm
Maximum slew rate	181 mA
Maximum supply voltage	3.46 V
Minimum supply voltage	3.14 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	20 mm
uPs/uCs/peripheral integrated circuit type	DIGITAL SIGNAL PROCESSOR, OTHER
Base Number Matches	1

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Freescale Semiconductor

Technical Data

Document Number: DSP56362

Rev. 4, 08/2006

DSP56362

24-Bit Audio Digital Signal Processor

Overview

Contents

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

Signal/Connection Descriptions . . . . . . . . . 2-1

Specifications . . . . . . . . . . . . . . . . . . . . . . . . 3-1

Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

Design Considerations . . . . . . . . . . . . . . . . 5-1

Ordering Information . . . . . . . . . . . . . . . . . . 6-1

Power Consumption Benchmark . . . . . . . . A-1

IBIS Model . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1

Freescale Semiconductor, Inc. designed the DSP56362

to support digital audio applications requiring digital

audio compression and decompression, sound field

processing, acoustic equalization, and other digital audio

algorithms. The DSP56362 uses the high performance,

single-clock-per-cycle DSP56300 core family of

programmable CMOS digital signal processors (DSPs)

combined with the audio signal processing capability of

the Freescale Symphony™ DSP family, as shown in

Figure 1-1.

This design provides a two-fold performance

increase over Freescale’s popular Symphony family of

DSPs while retaining code compatibility. Significant

architectural enhancements include a barrel shifter,

24-bit addressing, instruction cache, and direct memory

access (DMA). The DSP56362 offers 100 million

instructions per second (MIPS) using an internal 100

MHz clock at 3.3 V.

This document contains information on a new product. Specifications and information herein are subject to change without notice.

DSPB56362PV100 Related Products

	DSPB56362PV100	DSPB56362PV120	DSPF56362PV120
Description	IC,DSP,24-BIT,CMOS,QFP,144PIN,PLASTIC	IC,DSP,24-BIT,CMOS,QFP,144PIN,PLASTIC	IC,DSP,24-BIT,CMOS,QFP,144PIN,PLASTIC
Is it Rohs certified?	conform to	conform to	conform to
Maker	NXP	NXP	NXP
Parts packaging code	QFP	QFP	QFP
package instruction	20 X 20 MM, 0.50 MM PITCH, 1.40 MM HEIGHT, PLASTIC, LQFP-144	20 X 20 MM, 0.50 MM PITCH, 1.40 MM HEIGHT, PLASTIC, LQFP-144	20 X 20 MM, 0.50 MM PITCH, 1.40 MM HEIGHT, PLASTIC, LQFP-144
Contacts	144	144	144
Reach Compliance Code	unknown	unknown	unknown
ECCN code	3A991	3A991	3A991
Address bus width	18	18	18
barrel shifter	YES	YES	YES
bit size	24	24	24
boundary scan	YES	YES	YES
maximum clock frequency	100 MHz	120 MHz	120 MHz
External data bus width	24	24	24
Format	FIXED POINT	FIXED POINT	FIXED POINT
Internal bus architecture	MULTIPLE	MULTIPLE	MULTIPLE
JESD-30 code	S-PQFP-G144	S-PQFP-G144	S-PQFP-G144
length	20 mm	20 mm	20 mm
low power mode	YES	YES	YES
Humidity sensitivity level	3	3	3
Number of terminals	144	144	144
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	LFQFP	LFQFP	LFQFP
Encapsulate equivalent code	QFP144,.87SQ,20	QFP144,.87SQ,20	QFP144,.87SQ,20
Package shape	SQUARE	SQUARE	SQUARE
Package form	FLATPACK, LOW PROFILE, FINE PITCH	FLATPACK, LOW PROFILE, FINE PITCH	FLATPACK, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
power supply	3.3 V	3.3 V	3.3 V
Certification status	Not Qualified	Not Qualified	Not Qualified
RAM (number of words)	11264	11264	11264
Maximum seat height	1.6 mm	1.6 mm	1.6 mm
Maximum slew rate	181 mA	181 mA	181 mA
Maximum supply voltage	3.46 V	3.46 V	3.46 V
Minimum supply voltage	3.14 V	3.14 V	3.14 V
Nominal supply voltage	3.3 V	3.3 V	3.3 V
surface mount	YES	YES	YES
technology	CMOS	CMOS	CMOS
Terminal form	GULL WING	GULL WING	GULL WING
Terminal pitch	0.5 mm	0.5 mm	0.5 mm
Terminal location	QUAD	QUAD	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
width	20 mm	20 mm	20 mm
uPs/uCs/peripheral integrated circuit type	DIGITAL SIGNAL PROCESSOR, OTHER	DIGITAL SIGNAL PROCESSOR, OTHER	DIGITAL SIGNAL PROCESSOR, OTHER
Base Number Matches	1	1	-

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