M29F160BT
M29F160BB
16 Mbit (2Mb x8 or 1Mb x16, Boot Block)
Single Supply Flash Memory
PRELIMINARY DATA
s
SINGLE 5V±10% SUPPLY VOLTAGE for
PROGRAM, ERASE and READ OPERATIONS
ACCESS TIME: 55ns
PROGRAMMING TIME
– 8µs per Byte/Word typical
35 MEMORY BLOCKS
– 1 Boot Block (Top or Bottom Location)
– 2 Parameter and 32 Main Blocks
s
s
s
s
PROGRAM/ERASE CONTROLLER
– Embedded Byte/Word Program algorithm
– Embedded Multi-Block/Chip Erase algorithm
– Status Register Polling and Toggle Bits
– Ready/Busy Output Pin
TSOP48 (N)
12 x 20mm
s
ERASE SUSPEND and RESUME MODES
– Read and Program another Block during
Erase Suspend
Figure 1. Logic Diagram
s
UNLOCK BYPASS PROGRAM COMMAND
– Faster Production/Batch Programming
TEMPORARY BLOCK UNPROTECTION
MODE
LOW POWER CONSUMPTION
– Standby and Automatic Standby
100,000 PROGRAM/ERASE CYCLES per
BLOCK
20 YEARS DATA RETENTION
– Defectivity below 1 ppm/year
ELECTRONIC SIGNATURE
– Manufacturer Code: 0020h
– Top Device Code M29F160BT: 22CCh
– Bottom Device Code M29F160BB: 224Bh
A0-A19
W
E
G
RP
VCC
s
20
15
DQ0-DQ14
DQ15A–1
M29F160BT
M29F160BB
BYTE
RB
s
s
s
s
VSS
AI02920
March 2000
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
1/22
M29F160BT, M29F160BB
SUMMARY DESCRIPTION
The M29F160B is a 16Mbit (2Mb x8 or 1Mb x16)
non-volatile memory that can be read, erased and
reprogrammed. These operations can be per-
formed using a single 5V supply. On power-up the
memory defaults to its Read mode where it can be
read in the same way as a ROM or EPROM.
The memory is divided into blocks that can be
erased independently so it is possible to preserve
valid data while old data is erased. Each block can
be protected independently to prevent accidental
Program or Erase commands from modifying the
memory. Program and Erase commands are writ-
ten to the Command Interface of the memory. An
on-chip Program/Erase Controller simplifies the
process of programming or erasing the memory by
taking care of all of the special operations that are
required to update the memory contents. The end
of a program or erase operation can be detected
and any error conditions identified. The command
set required to control the memory is consistent
with JEDEC standards.
The blocks in the memory are asymmetrically ar-
ranged, see Tables 3 and 4, Block Addresses. The
first or last 64 Kbytes have been divided into four
additional blocks. The 16 Kbyte Boot Block can be
used for small initialization code to start the micro-
processor, the two 8 Kbyte Parameter Blocks can
be used for parameter storage and the remaining
32K is a small Main Block where the application
may be stored.
Chip Enable, Output Enable and Write Enable sig-
nals control the bus operation of the memory.
They allow simple connection to most micropro-
cessors, often without additional logic.
The memory is offered in a TSOP48 (12 x 20mm)
package and it is supplied with all the bits erased
(set to ’1’).
3/22
M29F160BT, M29F160BB
SIGNAL DESCRIPTIONS
See Figure 1, Logic Diagram, and Table 1, Signal
Names, for a brief overview of the signals connect-
ed to this device.
Address Inputs (A0-A19).
The Address Inputs
select the cells in the memory array to access dur-
ing Bus Read operations. During Bus Write opera-
tions they control the commands sent to the
Command Interface of the internal state machine.
Data Inputs/Outputs (DQ0-DQ7).
The Data In-
puts/Outputs output the data stored at the selected
address during a Bus Read operation. During Bus
Write operations they represent the commands
sent to the Command Interface of the internal state
machine.
Data Inputs/Outputs (DQ8-DQ14).
The Data In-
puts/Outputs output the data stored at the selected
address during a Bus Read operation when BYTE
is High, V
IH
. When BYTE is Low, V
IL
, these pins
are not used and are high impedance. During Bus
Write operations the Command Register does not
use these bits. When reading the Status Register
these
bits
should
be
ignored.
Data Input/Output or Address Input (DQ15A-1).
When BYTE is High, V
IH
, this pin behaves as a
Data Input/Output pin (as DQ8-DQ14). When
BYTE is Low, V
IL
, this pin behaves as an address
pin; DQ15A–1 Low will select the LSB of the Word
on the other addresses, DQ15A–1 High will select
the MSB. Throughout the text consider references
to the Data Input/Output to include this pin when
BYTE is High and references to the Address In-
puts to include this pin when BYTE is Low except
when stated explicitly otherwise.
Chip Enable (E).
The Chip Enable, E, activates
the memory, allowing Bus Read and Bus Write op-
erations to be performed. When Chip Enable is
High, V
IH
, all other pins are ignored.
Output Enable (G).
The Output Enable, G, con-
trols the Bus Read operation of the memory.
Write Enable (W).
The Write Enable, W, controls
the Bus Write operation of the memory’s Com-
mand Interface.
Reset/Block Temporary Unprotect (RP).
The Re-
set/Block Temporary Unprotect pin can be used to
apply a Hardware Reset to the memory or to tem-
porarily unprotect all blocks that have been pro-
tected.
A Hardware Reset is achieved by holding Reset/
Block Temporary Unprotect Low, V
IL
, for at least
t
PLPX
. After Reset/Block Temporary Unprotect
goes High, V
IH
, the memory will be ready for Bus
Read and Bus Write operations after t
PHEL
or
t
RHEL
, whichever occurs last. See the Ready/Busy
Output section, Table 17 and Figure 10, Reset/
Temporary Unprotect AC Characteristics for more
details.
Holding RP at V
ID
will temporarily unprotect the
protected blocks in the memory. Program and
Erase operations on all blocks will be possible.
The transition from V
IH
to V
ID
must be slower than
t
PHPHH
.
Ready/Busy Output (RB).
The Ready/Busy pin
is an open-drain output that can be used to identify
when the memory array can be read. Ready/Busy
is high-impedance during Read mode, Auto Select
mode and Erase Suspend mode.
After a Hardware Reset, Bus Read and Bus Write
operations cannot begin until Ready/Busy be-
comes high-impedance. See Table 17 and Figure
10, Reset/Temporary Unprotect AC Characteris-
tics.
During Program or Erase operations Ready/Busy
is Low, V
OL
. Ready/Busy will remain Low during
Read/Reset commands or Hardware Resets until
the memory is ready to enter Read mode.
The use of an open-drain output allows the Ready/
Busy pins from several memories to be connected
to a single pull-up resistor. A Low will then indicate
that one, or more, of the memories is busy.
Byte/Word Organization Select (BYTE).
The Byte/
Word Organization Select pin is used to switch be-
tween the 8-bit and 16-bit Bus modes of the mem-
ory. When Byte/Word Organization Select is Low,
V
IL
, the memory is in 8-bit mode, when it is High,
V
IH
, the memory is in 16-bit mode.
V
CC
Supply Voltage.
The V
CC
Supply Voltage
supplies the power for all operations (Read, Pro-
gram, Erase etc.).
The Command Interface is disabled when the V
CC
Supply Voltage is less than the Lockout Voltage,
V
LKO
. This prevents Bus Write operations from ac-
cidentally damaging the data during power up,
power down and power surges. If the Program/
Erase Controller is programming or erasing during
this time then the operation aborts and the memo-
ry contents being altered will be invalid.
A 0.1µF capacitor should be connected between
the V
CC
Supply Voltage pin and the V
SS
Ground
pin to decouple the current surges from the power
supply. The PCB track widths must be sufficient to
carry the currents required during program and
erase operations, I
CC4
.
Vss Ground.
The V
SS
Ground is the reference
for all voltage measurements.
5/22
Microcontroller MCU
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