M29F016B
16 Mbit (2Mb x8, Uniform Block) Single Supply Flash Memory
s
SINGLE 5V±10% SUPPLY VOLTAGE for
PROGRAM, ERASE and READ OPERATIONS
ACCESS TIME: 55ns
PROGRAMMING TIME
– 8µs by Byte typical
44
s
s
s
s
32 UNIFORM 64 Kbyte MEMORY BLOCKS
PROGRAM/ERASE CONTROLLER
– Embedded Byte Program algorithm
– Embedded Multi-Block/Chip Erase algorithm
– Status Register Polling and Toggle Bits
– Ready/Busy Output Pin
TSOP40 (N)
10 x 20mm
SO44 (M)
1
s
ERASE SUSPEND and RESUME MODES
– Read and Program another Block during
Erase Suspend
Figure 1. Logic Diagram
s
TEMPORARY BLOCK UNPROTECTION
MODE
UNLOCK BYPASS PROGRAM COMMAND
– Faster Production/Batch Programming
LOW POWER CONSUMPTION
– Standby and Automatic Standby
21
A0-A20
W
E
G
RP
M29F016B
RB
8
DQ0-DQ7
VCC
s
s
s
100,000 PROGRAM/ERASE CYCLES per
BLOCK
20 YEARS DATA RETENTION
– Defectivity below 1 ppm/year
ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Device Code: ADh
s
s
VSS
AI02964
March 2000
1/22
M29F016B
Figure 2. TSOP Connections
Figure 3. SO Connections
NC
RP
A11
A10
A9
A8
A7
A6
A5
A4
NC
NC
A3
A2
A1
A0
DQ0
DQ1
DQ2
DQ3
VSS
VSS
1
44
2
43
3
42
4
41
5
40
6
39
7
38
37
8
9
36
10
35
11
34
M29F016B
12
33
13
32
14
31
15
30
16
29
17
28
18
27
19
26
20
25
21
24
22
23
AI02965
A19
A18
A17
A16
A15
A14
A13
A12
E
VCC
NC
RP
A11
A10
A9
A8
A7
A6
A5
A4
1
40
A20
NC
W
G
RB
DQ7
DQ6
DQ5
DQ4
VCC
VSS
VSS
DQ3
DQ2
DQ1
DQ0
A0
A1
A2
A3
10
11
M29F016B
31
30
20
21
AI02969
VCC
E
A12
A13
A14
A15
A16
A17
A18
A19
NC
NC
A20
NC
W
G
RB
DQ7
DQ6
DQ5
DQ4
VCC
Table 1. Signal Names
A0-A20
DQ0-DQ7
E
G
W
RP
RB
V
CC
V
SS
NC
Address Inputs
Data Inputs/Outputs
Chip Enable
Output Enable
Write Enable
Reset/Block Temporary Unprotect
Ready/Busy Output
Supply Voltage
Ground
Not Connected Internally
2/22
M29F016B
Table 2. Absolute Maximum Ratings
(1)
Symbol
Parameter
Ambient Operating Temperature (Temperature Range Option 1)
T
A
Ambient Operating Temperature (Temperature Range Option 6)
Ambient Operating Temperature (Temperature Range Option 3)
T
BIAS
T
STG
V
IO (2)
V
CC
V
ID
Temperature Under Bias
Storage Temperature
Input or Output Voltage
Supply Voltage
Identification Voltage
Value
0 to 70
–40 to 85
–40 to 125
–50 to 125
–65 to 150
–0.6 to 6
–0.6 to 6
–0.6 to 13.5
Unit
°C
°C
°C
°C
°C
V
V
V
Note: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual-
ity documents.
2. Minimum Voltage may undershoot to –2V during transition and for less than 20ns during transitions.
SUMMARY DESCRIPTION
The M29F016B is a 16 Mbit (2Mb x8) non-volatile
memory that can be read, erased and repro-
grammed. These operations can be performed us-
ing a single 5V supply. On power-up the memory
defaults to its Read mode where it can be read in
the same way as a ROM or EPROM.
The memory is divided into blocks that can be
erased independently so it is possible to preserve
valid data while old data is erased. Blocks can be
protected in groups to prevent accidental Program
or Erase commands from modifying the memory.
Program and Erase commands are written to the
Command Interface of the memory. An on-chip
Program/Erase Controller simplifies the process of
programming or erasing the memory by taking
care of all of the special operations that are re-
quired to update the memory contents. The end of
a program or erase operation can be detected and
any error conditions identified. The command set
required to control the memory is consistent with
JEDEC standards.
Chip Enable, Output Enable and Write Enable sig-
nals control the bus operation of the memory.
They allow simple connection to most micropro-
cessors, often without additional logic.
The memory is offered in a TSOP40 (10 x 20mm)
and SO44 packages and it is supplied with all the
bits erased (set to ’1’).
3/22
M29F016B
Table 3. Uniform Block Addresses, M29F016B
#
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Size
(Kbytes)
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
Address Range
1F0000h-1FFFFFh
1E0000h-1EFFFFh
1D0000h-1DFFFFh
1C0000h-1CFFFFh
1B0000h-1BFFFFh
1A0000h-1AFFFFh
190000h-19FFFFh
180000h-18FFFFh
170000h-17FFFFh
160000h-16FFFFh
150000h-15FFFFh
140000h-14FFFFh
130000h-13FFFFh
120000h-12FFFFh
110000h-11FFFFh
100000h-10FFFFh
0F0000h-0FFFFFh
0E0000h-0EFFFFh
0D0000h-0DFFFFh
0C0000h-0CFFFFh
0B0000h-0BFFFFh
0A0000h-0AFFFFh
090000h-09FFFFh
080000h-08FFFFh
070000h-07FFFFh
060000h-06FFFFh
050000h-05FFFFh
040000h-04FFFFh
030000h-03FFFFh
020000h-02FFFFh
010000h-01FFFFh
000000h-00FFFFh
0
1
2
3
4
5
6
7
Protection
Group
SIGNAL DESCRIPTIONS
See Figure 1, Logic Diagram, and Table 1, Signal
Names, for a brief overview of the signals connect-
ed to this device.
Address Inputs (A0-A20).
The Address Inputs
select the cells in the memory array to access dur-
ing Bus Read operations. During Bus Write opera-
tions they control the commands sent to the
Command Interface of the internal state machine.
Data Inputs/Outputs (DQ0-DQ7).
The Data In-
puts/Outputs output the data stored at the selected
address during a Bus Read operation. During Bus
Write operations they represent the commands
sent to the Command Interface of the internal state
machine.
Chip Enable (E).
The Chip Enable, E, activates
the memory, allowing Bus Read and Bus Write op-
erations to be performed. When Chip Enable is
High, V
IH
, all other pins are ignored.
Output Enable (G).
The Output Enable, G, con-
trols the Bus Read operation of the memory.
Write Enable (W).
The Write Enable, W, controls
the Bus Write operation of the memory’s Com-
mand Interface.
Reset/Block Temporary Unprotect (RP).
The Re-
set/Block Temporary Unprotect pin can be used to
apply a Hardware Reset to the memory or to tem-
porarily unprotect all blocks that have been pro-
tected.
A Hardware Reset is achieved by holding Reset/
Block Temporary Unprotect Low, V
IL
, for at least
t
PLPX
. After Reset/Block Temporary Unprotect
goes High, V
IH
, the memory will be ready for Bus
Read and Bus Write operations after t
PHEL
or
t
RHEL
, whichever occurs last. See the Ready/Busy
Output section, Table 14 and Figure 11, Reset/
Temporary Unprotect AC Characteristics for more
details.
Holding RP at V
ID
will temporarily unprotect the
protected blocks in the memory. Program and
Erase operations on all blocks will be possible.
The transition from V
IH
to V
ID
must be slower than
t
PHPHH
.
Ready/Busy Output (RB).
The Ready/Busy pin
is an open-drain output that can be used to identify
when the memory array can be read. Ready/Busy
is high-impedance during Read mode, Auto Select
mode and Erase Suspend mode.
4/22
M29F016B
After a Hardware Reset, Bus Read and Bus Write
operations cannot begin until Ready/Busy be-
comes high-impedance. See Table 14 and Figure
11, Reset/Temporary Unprotect AC Characteris-
tics.
During Program or Erase operations Ready/Busy
is Low, V
OL
. Ready/Busy will remain Low during
Read/Reset commands or Hardware Resets until
the memory is ready to enter Read mode.
The use of an open-drain output allows the Ready/
Busy pins from several memories to be connected
to a single pull-up resistor. A Low will then indicate
that one, or more, of the memories is busy.
V
CC
Supply Voltage.
The V
CC
Supply Voltage
supplies the power for all operations (Read, Pro-
gram, Erase etc.).
The Command Interface is disabled when the V
CC
Supply Voltage is less than the Lockout Voltage,
V
LKO
. This prevents Bus Write operations from ac-
cidentally damaging the data during power up,
power down and power surges. If the Program/
Erase Controller is programming or erasing during
this time then the operation aborts and the memo-
ry contents being altered will be invalid.
A 0.1µF capacitor should be connected between
the V
CC
Supply Voltage pin and the V
SS
Ground
pin to decouple the current surges from the power
supply. The PCB track widths must be sufficient to
carry the currents required during program and
erase operations, I
CC4
.
V
SS
Ground.
The V
SS
Ground is the reference for
all voltage measurements.
BUS OPERATIONS
There are five standard bus operations that control
the device. These are Bus Read, Bus Write, Out-
put Disable, Standby and Automatic Standby. See
Table 4, Bus Operations, for a summary. Typically
glitches of less than 5ns on Chip Enable or Write
Enable are ignored by the memory and do not af-
fect bus operations.
Table 4. Bus Operations
Operation
Bus Read
Bus Write
Output Disable
Standby
Read Manufacturer
Code
Read Device Code
Note: X = V
IL
or V
IH
.
Bus Read.
Bus Read operations read from the
memory cells, or specific registers in the Com-
mand Interface. A valid Bus Read operation in-
volves setting the desired address on the Address
Inputs, applying a Low signal, V
IL
, to Chip Enable
and Output Enable and keeping Write Enable
High, V
IH
. The Data Inputs/Outputs will output the
value, see Figure 8, Read Mode AC Waveforms,
and Table 11, Read AC Characteristics, for details
of when the output becomes valid.
Bus Write.
Bus Write operations write to the
Command Interface. A valid Bus Write operation
begins by setting the desired address on the Ad-
dress Inputs. The Address Inputs are latched by
the Command Interface on the falling edge of Chip
Enable or Write Enable, whichever occurs last.
The Data Inputs/Outputs are latched by the Com-
mand Interface on the rising edge of Chip Enable
or Write Enable, whichever occurs first. Output En-
able must remain High, V
IH
, during the whole Bus
Write operation. See Figures 9 and 10, Write AC
Waveforms, and Tables 12 and 13, Write AC
Characteristics, for details of the timing require-
ments.
Output Disable.
The Data Inputs/Outputs are in
the high impedance state when Output Enable is
High, V
IH
.
Standby.
When Chip Enable is High, V
IH
, the
Data Inputs/Outputs pins are placed in the high-
impedance state and the Supply Current is re-
duced to the Standby level.
When Chip Enable is at V
IH
the Supply Current is
reduced to the TTL Standby Supply Current, I
CC2
.
To further reduce the Supply Current to the CMOS
Standby Supply Current, I
CC3
, Chip Enable should
be held within V
CC
±
0.2V. For Standby current
levels see Table 10, DC Characteristics.
During program or erase operations the memory
will continue to use the Program/Erase Supply
Current, I
CC4
, for Program or Erase operations un-
til the operation completes.
E
V
IL
V
IL
X
V
IH
V
IL
V
IL
G
V
IL
V
IH
V
IH
X
V
IL
V
IL
W
V
IH
V
IL
V
IH
X
V
IH
V
IH
Address Inpu ts
Cell Address
Command Address
X
X
A0 = V
IL
, A1 = V
IL
, A9 = V
ID
,
Others V
IL
or V
IH
A0 = V
IH
, A1 = V
IL
, A9 = V
ID
,
Others V
IL
or V
IH
Data
Inputs/Outpu ts
Data Output
Data Input
Hi-Z
Hi-Z
20h
ADh
5/22
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