IDT70T3599S166BFGI datasheet, PDF

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IDT70T3599S166BFGI: DescriptionDual-Port SRAM, 128KX36, 3.6ns, CMOS, CBGA208, 15 X 15 MM X 1.4 MM, 0.80 MM PITCH, GREEN, FPBGA-208; Categorystorage storage; File Size303KB，28 Pages; ManufacturerIDT (Integrated Device Technology); Environmental Compliance

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IDT70T3599S166BFGI Overview

Dual-Port SRAM, 128KX36, 3.6ns, CMOS, CBGA208, 15 X 15 MM X 1.4 MM, 0.80 MM PITCH, GREEN, FPBGA-208

IDT70T3599S166BFGI Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	IDT (Integrated Device Technology)
Parts packaging code	BGA
package instruction	LFBGA, BGA208,17X17,32
Contacts	208
Reach Compliance Code	unknown
ECCN code	3A991.B.2.A
Maximum access time	3.6 ns
Other features	PIPELINED OR FLOW-THROUGH ARCHITECTURE
Maximum clock frequency (fCLK)	166 MHz
I/O type	COMMON
JESD-30 code	S-CBGA-B208
JESD-609 code	e1
length	15 mm
memory density	4718592 bit
Memory IC Type	DUAL-PORT SRAM
memory width	36
Humidity sensitivity level	3
Number of functions	1
Number of ports	2
Number of terminals	208
word count	131072 words
character code	128000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	128KX36
Output characteristics	3-STATE
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	LFBGA
Encapsulate equivalent code	BGA208,17X17,32
Package shape	SQUARE
Package form	GRID ARRAY, LOW PROFILE, FINE PITCH
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	260
power supply	2.5,2.5/3.3 V
Certification status	Not Qualified
Maximum seat height	1.7 mm
Maximum standby current	0.02 A
Minimum standby current	2.4 V
Maximum slew rate	0.51 mA
Maximum supply voltage (Vsup)	2.6 V
Minimum supply voltage (Vsup)	2.4 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Silver/Copper (Sn/Ag/Cu)
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	30
width	15 mm
Base Number Matches	1

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Features:

◆

HIGH-SPEED 2.5V

256/128/64K x 36

IDT70T3519/99/89S

SYNCHRONOUS

DUAL-PORT STATIC RAM

WITH 3.3V OR 2.5V INTERFACE

◆

True Dual-Port memory cells which allow simultaneous

access of the same memory location

High-speed data access

– Commercial: 3.4 (200MHz)/3.6ns (166MHz)/

4.2ns (133MHz)(max.)

– Industrial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)

Selectable Pipelined or Flow-Through output mode

Counter enable and repeat features

Dual chip enables allow for depth expansion without

additional logic

Full synchronous operation on both ports

– 5ns cycle time, 200MHz operation (14Gbps bandwidth)

– Fast 3.4ns clock to data out

– 1.5ns setup to clock and 0.5ns hold on all control, data, and

address inputs @ 200MHz

– Data input, address, byte enable and control registers

– Self-timed write allows fast cycle time

◆

Interrupt and Collision Detection Flags

Separate byte controls for multiplexed bus and bus

matching compatibility

Dual Cycle Deselect (DCD) for Pipelined Output Mode

2.5V (±100mV) power supply for core

LVTTL compatible, selectable 3.3V (±150mV) or 2.5V

(±100mV) power supply for I/Os and control signals on

each port

Industrial temperature range (-40°C to +85°C) is

available at 166MHz and 133MHz

Available in a 256-pin Ball Grid Array (BGA), a 208-pin

Plastic Quad Flatpack (PQFP) and 208-pin fine pitch Ball

Grid Array (fpBGA)

Supports JTAG features compliant with IEEE 1149.1

Due to limited pin count JTAG is not supported on the 208-

pin PQFP package

Green parts available, see ordering information

Functional Block Diagram

FT/PIPE

1/0

0a 1a

0b 1b

0c 1c

0d 1d

1d 0d

1c 0c

1b 0b

1a 0a

1/0

FT/PIPE

R/W

1/0

B B

0 1

L L

B B

2 3

L L

B B

1 0

1/0

0 R

1 R

Dout0-8_L

Dout9-17_L

Dout18-26_L

Dout27-35_L

Dout0-8_R

Dout9-17_R

Dout18-26_R

Dout27-35_R

1d 0d 1c 0c 1b 0b 1a 0a

0a 1a 0b 1b 0c 1c 0d 1d

0/1

FT/PIPE

0/1

a bc d

d cba

256/128/64K x 36

MEMORY

ARRAY

I/O

- I/O

35L

Din_L

Din_R

I/O

- I/O

35R

CLK

17L

(1)

REPEAT

ADS

CNTEN

17R ( 1)

CLK

Counter/

Address

Reg.

ADDR_L

ADDR_R

Counter/

Address

Reg.

REPEAT

ADS

CNTEN

TDI

TCK

TMS

TRST

0 L

CE1L

R /

INTE RRUPT

COLLISION

DETECTION

LOGIC

0 R

CE1 R

JTAG

TD O

COL

INT

COL

INT

(2)

NOTES:

1. Address A

is a NC for the IDT70T3599. Also, Addresses A

and A

are NC's for the IDT70T3589.

2. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. All static inputs, i.e., PL/FTx and OPTx

and the sleep mode pins themselves (ZZx) are not affected during sleep mode.

CONTROL

LOGIC

(2)

5666 drw 01

JULY 2008

DSC 5666/9

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