Hitachi 16-Bit Single-Chip Microcomputer
H8S/2169F-ZTAT™
H8S/2149F-ZTAT™
H8S/2169
HD64F2169
H8S/2149
HD64F2149
Hardware Manual
ADE-602-190A
Rev. 2.0
02/21/01
Hitachi, Ltd.
Cautions
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consider normally foreseeable failure rates or failure modes in semiconductor devices and
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Preface
The H8S/2149 and H8S/2169 F-ZTAT™ comprises high-performance microcomputers with a 32-
bit H8S/2000 CPU core, and a set of on-chip supporting functions required for system
configuration.
The H8S/2000 CPU can execute basic instructions in one state, and is provided with sixteen
internal 16-bit general registers with a 32-bit configuration, and a concise and optimized
instruction set. The CPU can handle a 16-Mbyte linear address space (architecturally 4 Gbytes).
Programs based on the high-level language C can also be run efficiently.
Single-power-supply flash memory (F-ZTAT™*) is available, providing a quick and flexible
response to conditions from ramp-up through full-scale volume production, even for applications
with frequently changing specifications.
On-chip peripheral functions include a 16-bit free-running timer (FRT), 8-bit timer (TMR),
watchdog timer (WDT), two PWM timers (PWM and PWMX), a serial communication interface
(SCI, IrDA), I
2
C bus interface (IIC), PS/2-compatible keyboard buffer controller, host interface
(HIF:XBS and LPC), D/A converter (DAC), A/D converter (ADC), and I/O ports.
An on-chip data transfer controller (DTC) is also provided, enabling high-speed data transfer
without CPU intervention.
Use of the H8S/2149 and H8S/2169 F-ZTAT™ enables compact, high-performance systems to be
implemented easily. The comprehensive PC-related interface functions and 16
×
8 matrix key-
scan functions are ideal for applications such as notebook PC keyboard control and intelligent
battery and power supply control. In particular, the provision of two on-chip host interfaces—a
conventional X-BUS (ISA) interface and an LPC interface (a new standard)—provide flexible
support for PC systems in a period of transition.
This manual describes the hardware of the H8S/2149 and H8S/2169 F-ZTAT™. Refer to the
H8S/2600 Series and H8S/2000 Series Programming Manual
for a detailed description of the
instruction set.
This manual describes the hardware of the H8S/2149 and H8S/2169 F-ZTAT™. Although the
H8S/2169 is not explicitly mentioned in Section 2 to 7 or Section 9 to 22, the descriptions in these
Sections apply to both the H8S/2149 and H8S/2169.
Note: * F-ZTAT™ (Flexible-ZTAT) is a trademark of Hitachi, Ltd.
Main Revisions and Additions in this Edition
Page
All pages of
this manual
2 to 6
1. Overview
Item
Revision (See Manual for Details)
Amendments due to introduction of the H8S/2169
Table 1.1 Overview
CPU: operating frequency, and arithmetic operations
amended
PWM: maximum carrier frequency amended
PWMX: maximum carrier frequency amended
A/D converter: minimum conversion time amended
I/O ports: H8S/2169 added
Packages: TFP-144 (H8S/2169) added
Product lineup: amended
8
10
11
1.2 Internal Block Diagram Figure 1.1(b) Internal Block Diagram of H8S/2169 added
1.3.1 Pin Arrangement
Figure 1.2(b) H8S/2169 Pin Arrangement added
1.3.2 Pin Functions in Each Table 1.2(a) H8S/2149 Pin Functions in Each Operating
Operating Mode
Mode Pin No.9 : Pin function of Flash memory
programmer mode amended
1.3.2 Pin Functions in Each Table 1.2(b) H8S/2169 Pin Functions in Each Operating
Operating Mode
Mode
1.3.3 Pin Functions
Table 1.3 Pin Functions
Power (VCL), (VCCB) description amended
Clock (X1), (X2) description amended
Ports C to G description added
TFP-144 pin function added
16 to 21
22 to 30
All pages of
section 2
32
73
2.1.1 Features
2.9.4 On-Chip Supporting
Module Access Timing
(Internal I/O Register 3)
3.2.2 System Control
Register
Notes on TAS instruction added
Notes on STM/LDM instruction added
High-speed operation amended
Added
78
79
83
Address amended when bits 6 is 1
3.2.3 Bus Control Register Address amended when bits 1 and 0 are 1, respectively
3.4 Pin Function in Each
Operating Mode
3.5 Memory Map in Each
Operating Mode
Table 3.3 Pin Functions in Each Mode
Ports C to G added
Figure 3.1 H8S/2169 or H8S/2149 Memory Map in Each
Operating Mode amended
84, 85