M28C64C
M28C64X
64 Kbit (8Kb x8) Parallel EEPROM
FAST ACCESS TIME: 150ns
SINGLE 5V
±
10% SUPPLY VOLTAGE
LOW POWER CONSUMPTION
FAST WRITE CYCLE
– 32 Bytes Page Write Operation
– Byte or Page Write Cycle: 5ms
ENHANCED END OF WRITE DETECTION
– Ready/Busy Open Drain Output
(for M28C64C product only)
– Data Polling
– Toggle Bit
PAGE LOAD TIMER STATUS BIT
HIGH RELIABILITY SINGLE POLYSILICON,
CMOS TECHNOLOGY
– Endurance >100,000 Erase/Write Cycles
– Data Retention >40 Years
JEDEC APPROVED BYTEWIDE PIN OUT
DESCRIPTION
The M28C64C is an 8 Kbit x8 low power Parallel
EEPROM fabricated with STMicroelectronics pro-
prietary single polysilicon CMOS technology. The
device offers fast access time with low power dis-
sipation and requires a 5V power supply.
The circuit has been designed to offer a flexible
microcontroller interface featuring both hardware
and software handshakingmode with Ready/Busy,
Data Polling and Toggle Bit. The M28C64C sup-
ports 32 byte page write operation.
Table 1. Signal Names
A0 - A12
DQ0 - DQ7
W
E
G
RB
V
CC
V
SS
Address Input
Data Input / Output
Write Enable
Chip Enable
Output Enable
Ready / Busy
Supply Voltage
Ground
28
1
PDIP28 (P)
PLCC32 (K)
28
1
SO28 (MS)
300 mils
TSOP28 (N)
8 x13.4mm
Figure 1. Logic Diagram
VCC
13
A0-A12
8
DQ0-DQ7
W
E
M28C64C
RB
G
VSS
AI00746B
February 1999
1/15
M28C64C, M28C64X
Figure 2A. DIP Pin Connections
Figure 2B. LCC Pin Connections
AI00747C
DQ1
DQ2
VSS
DU
DQ3
DQ4
DQ5
AI00748D
RB
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
28
2
27
3
26
4
25
5
24
6
23
7
22
M28C64C
8
21
9
20
10
19
11
18
12
17
13
16
14
15
VCC
W
DU
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
A6
A5
A4
A3
A2
A1
A0
NC
DQ0
RB
DU
VCC
W
DU
1 32
A8
A9
A11
NC
G
A10
E
DQ7
DQ6
25
17
21
15
14
8
AI01016D
9
Warning:
DU = Don’t Use.
Warning:
NC = Not Connected, DU = Don’t Use.
Figure 2C. SO Pin Connections
Figure 2D. TSOP Pin Connections
RB
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
2
3
4
5
6
7
M28C64C
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
W
DU
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
G
A11
A9
A8
DU
W
VCC
RB
A12
A7
A6
A5
A4
A3
22
A7
A12
M28C64C
28
1
M28C64C
7
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
A1
A2
AI00876C
Warning:
DU = Don’t Use.
Warning:
DU = Don’t Use.
PIN DESCRITPION
Addresses (A0-A12).
The address inputs select
an 8-bit memory location during a read or write
operation.
Chip Enable (E).
The chip enable input must be
low to enable all read/write operations. When Chip
Enable is high, power consumption is reduced.
Output Enable (G).
The Output Enable input con-
trols the data output buffers and is used to initiate
read operations.
2/15
M28C64C, M28C64X
Table 2. Absolute Maximum Ratings
Symbol
T
A
T
STG
V
CC
V
IO
V
I
V
ESD
Parameter
Ambient Operating Temperature
Storage Temperature Range
Supply Voltage
Input/Output Voltage
Input Voltage
Electrostatic Discharge Voltage (Human Body model)
Value
– 40 to 125
– 65 to 150
– 0.3 to 6.5
– 0.3 to V
CC
+0.6
– 0.3 to 6.5
2000
Unit
°C
°
C
V
V
V
V
Note:
Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above
those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended
periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
Table 3. Operating Modes
Mode
Read
Write
Standby / Write Inhibit
Write Inhibit
Write Inhibit
Output Disable
Note:
X = V
IH
or V
IL
E
V
IL
V
IL
V
IH
X
X
X
G
V
IL
V
IH
X
X
V
IL
V
IH
W
V
IH
V
IL
X
V
IH
X
X
DQ0 - DQ7
Data Out
Data In
Hi-Z
Data Out or Hi-Z
Data Out or Hi-Z
Hi-Z
Data In/ Out (DQ0 - DQ7).
Data is written to or read
from the M28C64C through the I/O pins.
Write Enable (W).
The Write Enable input controls
the writing of data to the M28C64C.
Ready/Busy (RB).
Ready/Busy is an open drain
output that can be used to detect the end of the
internal write cycle.
OPERATION
In order to prevent data corruption and inadvertent
write operations during power-up, a Power On
Reset (POR) circuit resets all internal programming
cicuitry. Access to the memory in write mode is
allowed after a power-up as specified in Table 6.
Read
The M28C64C is accessed like a static RAM.
When E and G are low with W high, the data
addressed is presented on the I/O pins. The I/O
pins are high impedancewhen either G or E is high.
Write
Write operations are initiated when both W and E
are low and G is high.The M28C64C supports both
E and W controlled write cycles. The Address is
latched by the falling edge of E or W which ever
occurs last and the Data on the rising edge of E or
W which ever occurs first. Once initiated the write
operation is internally timed until completion.
Page Write
Page write allows up to 32 bytes to be consecu-
tively latched into the memory prior to initiating a
programming cycle. All bytes must be located in a
single page address, that is A5 - A12 must be the
same for all bytes. The page write can be initiated
during any byte write operation.
Following the first byte write instruction the host
may send another address and data up to a maxi-
mum of 100µs after the rising edge of E or W which
ever occurs first (t
BLC
). If a transition of E or W is
not detected within 100
µ
s, the internal program-
ming cycle will start.
3/15
M28C64C, M28C64X
Figure 3. Block Diagram
RB
E
G
W
VPP GEN
RESET
ATD & CONTROL LOGIC
X DECODE
A5-A12
(Page Address)
ADDRESS
LATCH
64K ARRAY
A0-A4
ADDRESS
LATCH
Y DECODE
SENSE AND DATA LATCH
I/O BUFFERS
PAGE LOAD
TIMER STATUS
TOGGLE BIT
DATA POLLING
AI00877C
DQ0-DQ7
Microcontroller Control Interface
The M28C64C provides two write operation status
bits and one status pin that can be used to minimize
the system write cycle. These signals are available
on the I/O port bits DQ7 or DQ6 of the memory
during programming cycle only, or as the RB signal
on a separate pin.
Figure 4. Status Bit Assignment
DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
DP
TB
PLTS Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
DP = Data Polling
TB = Toggle Bit
PLTS = Page Load Timer Status
Data Polling bit (DQ7).
During the internal write
cycle, any attempt to read the last byte written will
produce on DQ7 the complementary value of the
previously latched bit. Once the write cycle is fin-
ished the true logic value appears on DQ7 in the
read cycle.
4/15
Toggle bit (DQ6).
The M28C64C offers another
way for determining when the internal write cycle
is completed. Duringthe internal Erase/Write cycle,
DQ6 will toggle from ”0” to ”1” and ”1” to ”0” (the
first read value is ”0”) on subsequent attempts to
read any address in the memory. When the internal
cycle is completed the toggling will stop and the
device will be accessible for a new Read or Write
operation.
Page Load Timer Status bit (DQ5).
In the Page
Write mode data may be latched by E or W up to
100µs after the previous byte. Up to 32 bytes may
be input. The Data output (DQ5) indicates the
status of the internal Page Load Timer. DQ5 may
be read by asserting Output Enable Low (t
PLTS
).
DQ5 Low indicates the timer is running, High
indicates time-out after which the write cycle will
start and no new data may be input.
Ready/Busy pin.
The RB pin provides a signal at
its open drain output which is low during the
erase/write cycle, but which is released at the
completion of the programming cycle.
M28C64C, M28C64X
Table 4. AC Measurement Conditions
Input Rise and Fall Times
Input Pulse Voltages
Input and Output Timing Ref. Voltages
≤
20ns
0.4V to 2.4V
0.8V to 2.0V
1N914
Figure 6. AC Testing Equivalent Load Circuit
1.3V
Note that Output Hi-Z is defined as the point where data is no
longer driven.
3.3kΩ
Figure 5. AC Testing Input Output Waveforms
2.4V
DEVICE
UNDER
TEST
CL = 30pF
OUT
2.0V
0.8V
AI00826
0.4V
CL includes JIG capacitance
AI01129
Table 5. Capacitance
(1)
(T
A
= 25
°C,
f = 1 MHz )
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output Capacitance
Test Condition
V
IN
= 0V
V
OUT
= 0V
Min
Max
6
12
Unit
pF
pF
Note:
1. Sampled only, not 100% tested.
Table 6. Read Mode DC Characteristics
(T
A
= 0 to 70°C or –40 to 85°C, V
CC
= 4.5V to 5.5V)
Symbol
I
LI
I
LO
I
CC (1)
I
CC1
I
CC2
(1)
(1)
Parameter
Input Leakage Current
Output Leakage Current
Supply Current (TTL and CMOS inputs)
Supply Current (Standby) TTL
Supply Current (Standby) CMOS
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Test Condition
0V
≤
V
IN
≤
V
CC
0V
≤
V
IN
≤
V
CC
E = V
IL
, G = V
IL
, f = 5 MHz
E = V
IH
E > V
CC
–0.3V
Min
Max
10
10
30
2
100
Unit
µ
A
µA
mA
mA
µ
A
V
V
V
V
V
IL
V
IH
V
OL
V
OH
– 0.3
2
I
OL
= 2.1 mA
I
OH
= –400
µ
A
2.4
0.8
V
CC
+0.5
0.4
Note:
1. All I/O’s open circuit.
Table 7. Power Up Timing
(1)
(T
A
=
0 to 70
°
C or –40 to 85
°
C, V
CC
= 4.5V to 5.5V)
Symbol
t
PUR
t
PUW
Parameter
Time Delay to Read Operation
Time Delay to Write Operation
Min
1
10
Max
Unit
µs
ms
Note:
1. Sampled only, not 100% tested.
5/15
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